ML4802
FUNCTIONAL DESCRIPTION (Continued)
In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 6
shows a leading edge control scheme.
TYPICAL APPLICATIONS
Figure 7 is the application circuit for a complete 100W
power factor corrected power supply, designed using the
methods and general topology detailed in Application
Note 33.
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the
first stage is reduced. Calculation and evaluation have
shown that the 120Hz component of the PFC’s output
ripple voltage can be reduced by as much as 30% using
this method.
SW2
SW1
I2
I3
I4
L1
I1
+
VIN
RL
DC
RAMP
C1
VEAO
U3
EA
+
–
REF
VEAO
TIME
DFF
CMP
VSW1
+
–
R
RAMP
CLK
Q
Q
U1
OSC
U4
D
U2
CLK
TIME
Figure 6. Leading/Trailing Edge Control Scheme
Datasheet August 2000
12
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
