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ML4801 参数 Datasheet PDF下载

ML4801图片预览
型号: ML4801
PDF下载: 下载PDF文件 查看货源
内容描述: 变量前馈PFC / PWM控制器组合 [Variable Feedforward PFC/PWM Controller Combo]
分类和应用: 功率因数校正控制器
文件页数/大小: 14 页 / 231 K
品牌: MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
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ML4801  
LEADING/TRAILING MODULATION  
Conventional Pulse Width Modulation (PWM) techniques  
employ trailing edge modulation in which the switch will  
turn on right after the trailing edge of the system clock.  
The error amplifier output voltage is then compared with  
the modulating ramp. When the modulating ramp reaches  
the level of the error amplifier output voltage, the switch  
will be turned OFF. When the switch is ON, the inductor  
current will ramp up. The effective duty cycle of the  
trailing edge modulation is determined during the ON  
time of the switch. Figure 3 shows a typical trailing edge  
control scheme.  
One of the advantages of this control technique is that it  
requires only one system clock. Switch 1 (SW1) turns off  
and switch 2 (SW2) turns on at the same instant to  
minimize the momentary “no-load” period, thus lowering  
ripple voltage generated by the switching action. With  
such synchronized switching, the ripple voltage of the  
first stage is reduced. Calculation and evaluation have  
shown that the 120Hz component of the PFCs output  
ripple voltage can be reduced by as much as 30% using  
this method.  
In the case of leading edge modulation, the switch is  
turned OFF right at the leading edge of the system clock.  
When the modulating ramp reaches the level of the error  
amplifier output voltage, the switch will be turned ON.  
The effective duty-cycle of the leading edge modulation  
is determined during the OFF time of the switch. Figure 4  
shows a leading edge control scheme.  
TYPICAL APPLICATIONS  
Figure 9 is the application circuit for a complete 100W  
power factor corrected power supply, designed using the  
methods and general topology detailed in Application  
Note 33.  
SW2  
SW1  
SW2  
SW1  
I2  
I3  
I4  
I2  
I3  
I4  
L1  
I1  
L1  
I1  
+
+
RL  
VIN  
VIN  
RL  
DC  
DC  
RAMP  
RAMP  
C1  
C1  
VEAO  
VEAO  
REF  
U3  
EA  
U3  
EA  
+
+
REF  
VEAO  
TIME  
TIME  
DFF  
DFF  
U2  
CMP  
VSW1  
VSW1  
+
+
R
RAMP  
CLK  
Q
Q
R
D
RAMP  
CLK  
Q
U1  
U1  
OSC  
U4  
D
OSC  
U4  
U2  
Q
CLK  
CLK  
TIME  
TIME  
Figure 3. Typical Trailing Edge Control Scheme  
Figure 4. Leading/Trailing Edge Control Scheme  
10