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ML4801IP 参数 Datasheet PDF下载

ML4801IP图片预览
型号: ML4801IP
PDF下载: 下载PDF文件 查看货源
内容描述: 变量前馈PFC / PWM控制器组合 [Variable Feedforward PFC/PWM Controller Combo]
分类和应用: 功率因数校正光电二极管控制器
文件页数/大小: 14 页 / 231 K
品牌: MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
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ML4801
FUNCTIONAL DESCRIPTION
1
t
RAMP
(Continued)
This voltage may be derived either by a current sensing
resistor or a current transformer.
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 25µA
supplies the charging current for the capacitor, and start-
up of the PWM begins at 1.25V. Start-up delay can be
programmed by the following equation:
C
SS
=
t
DELAY
×
25
µ
A
.
125V
operating frequency can typically be approximated by:
f
OSC
=
(5)
EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at:
f
OSC
=
100kHz
=
1
t
RAMP
-
5
t
RAMP
=
0.51
´
R
T
´
C
T
=
1
´
10
(6)
Solving for R
T
x C
T
yields 2 x 10
-4
. Selecting standard
components values, C
T
= 270pF, and R
T
= 36.5kΩ.
PWM SECTION
The PWM section of the ML4801 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, and that the PWM stage is
optimized for current-mode operation. In the ML4801, the
operating frequency of the PFC section is fixed at 1/2 of
the PWM's operating frequency. This is done through the
use of a 2:1 digital frequency divider ("T" flip-flop) linking
the two functional sections of the IC.
No voltage error amplifier is included in the PWM stage
of the ML4801, as this function is generally performed on
the output side of the PWM’s isolation boundary. To
facilitate the design of optocoupler feedback circuitry, an
offset has been built into the PWM’s RAMP 2 input which
allows V
DC
to command a zero percent duty cycle for
input voltages below 1.25V.
PWM Current Limit
The RAMP 2 pin provides a direct input to the cycle-by-
cycle current limiter for the PWM section. Should the
input voltage at this pin ever exceed 1.5V, the output of
the PWM will be disabled until the output flip-flop is reset
by the clock pulse at the start of the next PWM power
cycle.
V
IN
OK Comparator
The V
IN
OK comparator monitors the DC output of the
PFC and inhibits the PWM if this voltage on V
FB
is less
than its nominal 2.5V. Once this voltage reaches 2.5V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start
commences.
PWM Control (RAMP 2)
In addition to its PWM current limit function, RAMP 2 is
used as the sampling point for a voltage representing the
current in the primary of the PWM’s output transformer.
where C
SS
is the required soft start capacitance, and
t
DELAY
is the desired start-up delay.
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.
Solving for the minimum value of C
SS
:
C
SS
=
5ms
×
25
µ
A
=
100nF
125V
.
Generating V
CC
The ML4801 is a voltage-fed part. It requires an external
15V±10% or better Zener shunt voltage regulator, or some
other V
CC
regulator, to maintain the voltage supplied to
the part at 15V nominal. This allows a low power
dissipation while at the same time delivering 13V
nominal of gate drive at the PWM OUT and PFC OUT
outputs. If using a Zener diode, it is important to limit the
current through the Zener to avoid overheating or
destroying it. This can be easily done with a single resistor
in series with the Vcc pin, returned to a bias supply of
typically 18V to 20V. The resistor’s value must be chosen
to meet the operating current requirement of the ML4801
itself (8.5mA max.) plus the current required by the two
gate driver outputs.
EXAMPLE:
With a V
BIAS
of 20V, a V
CC
limit of 16.5V (max) and
driving a total gate charge of 110nC at 100kHz (1 IRF840
MOSFET and 2 IRF830 MOSFETs), the gate driver current
required is:
I
GATEDRIVE
=
100kHz
´
110nC
=
11
mA
R
BIAS
=
20V
-
16.5V
=
180
mA
7.5mA
+
11
The ML4801 should be locally bypassed with a 10nF and
a 1µF ceramic capacitor. In most applications, an
electrolytic capacitor of between 33µF and 100µF is also
required across the part, both for filtering and as part of
the start-up bootstrap circuitry.
9