ML4664/ML4669
SYSTEM DESCRIPTION (Continued)
Link test pulses that do not occur within at most 25 to
150ms of each other are not considered consecutive.
In addition, detected pulses that occur within a time
between 2 to 7ms of a previous pulse will be considered
as noise by the link test circuitry, and will reset the count
of consecutive link pulses to zero.
The POLDIS status pin is updated only when four
consecutive frames are received with the same Start of
Idle polarity. In the case where the part is powered up
with the receive polarity reversed and no frames are
received, the part will go into link test fail without
reflecting a reverse polarity condition. If five consecutive
revised link pulses are then received, the polarity will
reverse and the device will come out of Link Test Fail.
If the ML4664 enters the link test fail state, both link
pulses at the twisted pair transmitter, and idle at the
optical transmitter will continue to be sent. Data will not
be sent at either transmitter.
TP TRANSMISSION
The TP transmit function consists of detecting the
presence of data from the OP inputs, OPINP and OPINN
and driving that data onto the transmit twisted pair
(TPOUTP, TPOUTN). A positive signal on the OPINP lead
relative to the OPINN lead will result in a positive signal
on the TPOUTP lead of the chip with respect to the
TPOUTN lead.
If the ML4669 enters the link test fail state, idle will not
be sent at the optical transmitter. Data will not be sent at
either transmitter. However, link pulses may still be sent
at the twisted pair transmitter, depending on the optical
inputs. See Table 1.
POLARLITY CIRCUITRY
Before data will be transmitted onto the twisted pair from
the OP inputs, it must exceed the squelch requirements
for the OP inputs. The OP squelch circuit serves the
function of preventing any noise from being transmitted
onto the twisted pair.
The ML4664/ML4669 offers automatic polarity correction.
The POLDIS pin is used to report the status of the receive
pair polarity. This pin is high when the polarity is correct,
and low when the polarity is reversed. If this pin is
grounded, the polarity correction circuit is disabled.
The output stage of the transmitter is a current mode
switch which develops the output voltage by driving
current through the terminating resistor and the output
filter. The transmitter employs a center tap 2:1 transformer
Polarity Detection — The internal circuitry uses the start
of idle signal to determine the receive polarity. With the
correct receive polarity, the Start of Idle signal (the end of
the frame) will remain above 300mV for more than
160ns. If the polarity is reversed, the Start of Idle signal
will end with a negative voltage.
where the center tap is tied to V (+5V). While one pin
CC
of the transmit pair (TPOUTP, TPOUTN) is pulled low, the
other pin floats. The output pins to the twisted pair wires,
BINARY
0
1
1
1
0
0
1
1
0
TxTP+
TxTP–
OUTPUT AFTER
TRANSMIT FILTER
INPUT INTO
RECEIVER
Figure 9. Transmit Pre-Equalization Waveform
10
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
