ML4621
PIN DESCRIPTION (Pin Number in Parenthesis is for DIP Version)
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1 (1) ECL LINK MON ECL link monitor output. Signal
14(12) CMP–
Comparator input pin. Open base
configuration relies on the DC
bias of the amp output to set the
proper DC operating voltage.
Reestablish voltage if filtering is
is low when the V + and V –
IN
IN
inputs exceed the minimum
threshold set by a voltage on
ADJ. Signal is high when
V
TH
input signal level is below that
used between V – and CMP–.
OUT
threshold.
16(13) ECL–
ECL comparator negative output.
ECL comparator positive outout.
2 (2) TTL LINK MON TTL link monitor output. Same
logic function as the ECL LINK
17(14) ECL+
MON. Capable of driving a
10mA LED indicator. This pin is
normally tied to CMP ENABLE.
18(15) GND TTL
Negative supply for the TTL
comparator stage. If the TTL
output is not necessary, connect
3 (3) CMP ENABLE Low voltage at this TTL input
enables both the ECL and TTL
outputs. A high TTL voltage
GND TTL and V TTL to V
.
CC
CC
19(16) V TTL
Positive supply for the TTL
comparator stage. If the TTL
CC
disables the comparator output
with ECL+ high, ECL– low, and
TTL OUT high.
output is not necessary, connect
GND TTL and V TTL to V
.
CC
CC
5 (4)
V
–
This input should be capacitively
coupled to the input source or to
ground. (Input resistance is
approximately 8kΩ).
20(17) TTL OUT
21(18) GND
TTL data output (totem pole type
output stage).
IN
Negative supply. Connect to –
5.2V for ECL operation, or to
source ground for TTL operation.
6 (5) V +
This input should be capacitively
coupled to the input source or to
ground. (Input resistance is
approximately 8kΩ).
IN
22(19) V ADJ
This input sets the minimum
amplitude of the input signal
required to cause the link
monitors to go low.
TH
8 (6) VDC
An external capacitor on this pin
integrates an error signal which
nulls the offset of the input
amplifier. If the DC feedback
loop is not being used, this pin
23(20) V
24(21) C
A 2.5V reference with respect to
GND.
REF
should be connected to V
.
A capacitor from this pin to GND
determines the link monitor
response time.
REF
PEAK
9 (7) CF2
10 (8) CF1
A capacitor from this pin to
ground controls the maximum
bandwidth of the amplifier to
accommodate lower operating
frequencies.
26(22) I
Current into an internal diode
connected between this pin and
GND is turned around and pulled
SET
from C
connected to I
. This pin is normally
PEAK
The capacitor on this pin should
match the one on CF2.
.
NOM
27(23) I
Sets a current of approximately
NO M
11 (9) V
12 (10) V
-
Negative output of the amplifier,
which is normally tied to CMP–.
125µA when connected to I
.
OUT
SET
28(24) V
Positive supply. Connect to
source ground for ECL operation,
or to 5V for TTL operation.
CC
+
OUT
Positive output of the amplifier,
which is normally tied to CMP+.
13 (11) CMP+
Comparator input pin. Open base
configuration relies on the DC
bias of the amp output to set
proper DC operating voltage.
Reestablish voltage if filtering is
used between V + and CMP+.
OUT
3
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
