ML4423
Current Limit
OUTPUTDRIVE
Motor current is sensed on I
be selected so that
(pin 16). R
should
(4)
SENSE
LIMIT
The 6 output drivers of the ML4423 drive the H and L
outputs from 0 to 12 volts (with pin 25 tied to V +(12V)).
CC
The outputs will drive about 10mA and are designed to
drive output buffers and high side drivers requiring 12V
swings. The ML4423 provides lower current 0 to 5V drive
for high/low side drivers requiring 5V input signal swings
with pin 25 left unconnected.
0.5V
R
LIMIT
=
I
MAX
For a 2A current limit, R
= 0.25W. The 1kW resistor
LIMIT
and 330pF capacitor filter (shown in figure 3) filter the
high frequency flyback pulses (due to the freewheeling
diode recovery currents) occurring at the output. When
PROGRAMMABLE DEADTIME
A dead time circuit is provided to prevent shoot through
currents in the power output stage. The dead time is
controlled by a resistor to ground on R (pin 9). The dead
time selected should be large enough to prevent cross
conduction between the upper and lower power devices
of each inverter phase leg.
I
is reached the output power will be turned off for
MAX
the remainder of the current PWM cycle, which is
asynchronous with the sinewave frequency. Thus current
limit is fixed-period with variable duty cycle.
DT
PWM SINE Controller
−11
t
= 1.2×10
R
(
DB
(6)
)
DEAD
This circuit block compares the sinewaves at SINE and
A
SINE to the sampled inputs SENSE –SENSE and
B
A
C
With f
= 25kHz, the PWM period is 40ms. With R
= 2ms (~5%).
SENSE –SENSE , respectively. The PWM loop then
PWM
DB
B
C
= 166k, t
drives the outputs to force these “differential” waveforms
DEAD
to equal the internal reference waveforms at SINE and
A
C
and C
GM2
SINE . The differential signals SENSE –SENSE and
GM1
B
A
C
SENSE –SENSE will be approximately 1.7 volts zero-
B
C
These two external capacitors to ground each set a pole in
the forward path of the feedback loop in conjunction with
a g of 1/650W. The pole should be placed at a frequency
higher than the PWM frequency.
peak maximum. The signals at these pins should be
filtered to remove the PWM frequency. The high voltages
at the motor terminals are divided down to 1.7V to
provide voltage feedback to the controller. In figure 3,
m
the resistors to ground from SENSE (pin 1) and SENSE
A
B
(pin 3) should be 1kW. SENSE (pin 2) should have a
C
g
m
> f
500W to ground because it has 1/2 the input impedance
of the other 2 inputs. The 0.15mF capacitors to ground on
PWM
(7)
2πC
g
m
SENSE and SENSE and the 0.3mF capacitor to ground
A
B
on SENSE will create a 1kHz low pass filter at these
C
PEAK
APPLICATION
inputs. V
on the motor is set by the divider ratios.
For the values shown in figure 3:
The ML4423 provides all the signals necessary to drive
the output power stage connected to the motor. The
components around the ML4423 for a typical application
are shown in figure 3. The motor DC supply voltage
should be greater than the largest signal waveform
required or output clipping may result. Figure 4 shows an
alternate circuit using the IR2118.
(V
= 4.4V)
SPEED
99k +1k
V
PEAK
= 1.7V
1k
49.5k + 500
= 1.7V
(5)
500
= 170V
6
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
