ML4411/ML4411A
BRAKING
As shown in figure 9, the braking circuit pulls the N-
Channel MOSFET gates high when BRAKE falls below a
1.4V threshold. After a power failure, C
DLY
is discharged
slowly through R
DLY
providing a delay for retract to occur
before the braking circuit is activated. The N-Channel
buffer (B1) tri-states when the BRAKE pin reaches 2.1V to
ensure that no charge from C
BRK
is lost through the pull-
down transistor in B1. To brake the motor with external
signals, first disable power by pulling pin 8 low, then pull
pin 26 below 1.4V using an open drain (or diode isolated)
output.
The bias current for the Braking circuits comes from
VCC2. When the N-Channel MOSFETs turn on, no
additional power is generated for VCC2 (motor back-EMF
rectified through out the MOSFET body diodes). After
VCC2 drops below 4V, Q2 turns off. Continued braking
relies on the C
GS
of the N-Channel MOSFETs to sustain
the MOSFET gate enhancement voltage.
60
50
40
T
OFF
(µs)
30
20
10
0
0
0.01
0.02
C
OS
0.03
0.04
0.05
Figure 8. I
LIMIT
Output Off-Time vs. C
OS
.
VCC2
P1 . . . P3
16K
POWER FAIL
17
4.5K
+5
VCC2 – 3V
UVLO
COMM. LOGIC
DIS PWR
R
DLY
+
VCC2
26
C
DLY
BRAKE
+
A4
1.4V
–
COMMUTATION
LOGIC
B1
UVLO
VIN
TRI-
ST.
N1 . . . N3
R
SENSE
I
LIMIT
Q
+
A3
28
I
CMD
–
ONE
SHOT
C
OS
13
VCC
+
12
I
SENSE
A
V
= 5
A1
1K
–
A2
C
OTA
2.1V
–
A5
C
BRK
Q1
7
VCC2
Q2
–
VCC
VCC2
+
A6
P3 ONLY
8
DIS PWR
27
6
Figure 9. Current Control, Output Drive and Braking Circuits.
9
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
