ML4411/ML4411A
FUNCTIONAL DESCRIPTION
The ML4411 provides closed-loop commutation for
3-phase brushless motors. To accomplish this task, a VCO,
integrating Back-EMF Sampling error amplifier and
sequencer form a phase-locked loop, locking the VCO to
the back-EMF of the motor. The IC also contains circuitry
to control motor current with either linear or constant off-
time PWM modes. Braking and power fail detection
functions are also provided on chip. The ML4411 is
designed to drive external power transistors (N-channel
sinking transistors and PNP sourcing transistors) directly.
maximum voltage at any PH input does not exceed VCC.
NEUTRAL
Start-up sequencing and motor speed control are
accomplished by a microcontroller. Speed sensing is
accomplished by monitoring the output of the VCO,
which will be a signal which is phased-locked to the
commutation frequency of the motor.
0
60
120
180
240
300
0
BACK-EMF SENSING AND COMMUTATOR
Figure 2. Typical motor phase waveform with Back-EMF
superimposed (Ideal Commutation)
The ML4411 contains a patented back-EMF sensing
circuit which samples the phase which is not energized
(Shaded area in figure 2) to determine whether to increase
or decrease the commutator (VCO) frequency. A late
commutation causes the error amplifier to charge the
filter (RC) on pin 20, increasing the VCO input while
early
VCO AND PHASE DETECTOR CALCULATIONS
The VCO should be set so that at the maximum frequency
of operation (the running speed of the motor) the VCO
control voltage will be no higher than VCC
VCO maximum frequency will be:
– 1V. The
MIN
commutation causes pin 20 discharge. Analog speed
control loops can use pin 20 as a speed feedback voltage.
F
= 0.05× POLES ×RPM
MAX
The input impedance of the three PH inputs is about 8Ký
to GND. When operating with a higher voltage motor, the
PH inputs should be divided down in voltage so that the
where POLES is the number of poles on the motor and
RPM is the maximum motor speed in Revolutions Per
ROTATION
SENSE
+
–
ΦA
+
NEUTRAL
SIMULATOR
Va – Vb
8K
I
RC
=
ΦB
ΦC
ΦA + ΦB + ΦC
I(PIN 21)
6
a
+
–
LOOP FILTER
R
SIGN
CHANGER
RC
b
8K
8K
MULTIPLEXER
C1
C2
COMMUTATION
LOGIC
VCO
VCO /TACH OUT
DIS PWR
FIGURE 1. BACK EMKF sensing block diagram
5