ML2281, ML2282, ML2284, ML2288
17
18
DI*
CS
D
R
R
R
R
R
5-BIT SHIFT-REGISTER
CS
ODD/
START SGL/DIF
SELECT 1
SELECT 0
SIGN
C
START
16
13
CLK
SE*
MUX
ADDRESS
V
CC
NOTE 1
+
NOTE 1
CS
SARS*
15
1
2
3
4
5
6
7
8
9
CH0*
CH1*
CH2
Σ
T
CS
D
–
C
R
TIME
DELAY
Q
D
D
Q
DSTART 2
CH3
ANALOG
MUX
(EQUIVALENT)
+
–
DSTART 1
C
R
CS
DEOC
CH4*
CH5*
CH6*
CH7*
COM*
D
Q
C
CS
C
R
R
CS
CS
C
14
CS
EOC
Q
DO
COMP
D
B7
B6
B5
R
R
C
C
12
20
V
REF
R
TO INTERNAL
CIRCUITRY
SAR
LOGIC
AND
9-BIT
SHIFT
V
CC
B4
B3
B2
B1
LADDER
AND
DECODER
REGISTER
INPUT
V
CC
V+*
LATCH
13
16
17
18
TO
INTERNAL
CIRCUITS
7V SHUNT
REGULATOR
DGND*
B0
EOC
COMP
INPUT PROTECTION—ALL LOGIC INPUTS
AGND*
LSB FIRST
MSB FIRST
PARALLEL XFR
TO SHIFT REGISTER
*SOME OF THESE FUNCTIONS/PINS ARE NOT AVAILABLE WITH OTHER OPTIONS.
NOTE 1: FOR THE ML2284 DI IS INPUT DIRECTLY TO THE D INPUT OF SELECT 1. SELECT 0 IS FORCED TO A “1”. FOR THE ML2282, DI IS INPUT DIRECTLY TO THE D
INPUT OF ODD/SIGN. SELECT 0 IS FORCED TO A “1” AND SELECT 1 IS FORCED TO A “0”.
Figure 6. ML2288 Functional Block Diagram
11
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
