ML2281, ML2282, ML2284, ML2288
ML2288 Timing
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CLOCK (CLK)
t
OUTPUT DATA
SET-UP
ADDRESS MUX
CHIP SELECT (CS)
START ODD/ SELECT
BIT SIGN BIT 0
DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE)
DATA IN (DI)
SELECT
BIT 1
SGL/DIF
A/D CONVERSION IN PROCESS
SAR STATUS (SARS)
HI-Z
HI-Z
HI-Z
MSB FIRST DATA
LSB FIRST DATA
SE = “0”
DATA OUT (DO)
HI-Z
7
6
5
4
3
2
1
1
0
1
2
3
4
5
6
7
(MSB)
(LSB)
(MSB)
SE
t
SET-UP
USING SE
TO CONTROL
LSB FIRST
MSB FIRST DATA
DATA HELD
LSB FIRST DATA
OUTPUT
DO
HI-Z
SAMPLE & HOLD
ACQUISITION (t
HI-Z
7
6
5
4
3
2
0
1
2
3
4
5
6
7
(MSB)
(LSB)
(MSB)
)
ACQ
Figure 2. Timing Diagrams (Continued)
1.0
V
= 5V
= 5V
CC
V
REF
0.75
0.5
0.25
0
125 C
–55 C
25 C
0
0.01
0.1
1
CLOCK FREQUENCY (MHz)
Figure 3. Linearity Error vs f
CLK
9
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
