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ML2283BCP 参数 Datasheet PDF下载

ML2283BCP图片预览
型号: ML2283BCP
PDF下载: 下载PDF文件 查看货源
内容描述: 串行I / O 8位A / D转换器 [Serial I/O 8-Bit A/D Converters]
分类和应用: 转换器光电二极管
文件页数/大小: 20 页 / 359 K
品牌: MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
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ML2280, ML2283  
ANALOG INPUTS AND SAMPLE/HOLD  
ZERO ERROR ADJUSTMENT  
An important feature of the ML2280 and ML2283 is that  
they can be located at the source of the analog signal and  
then communicate with a controlling µP with just a few  
wires. This avoids bussing the analog inputs long distances  
and thus reduces noise pickup on these analog lines.  
However, in some cases, the analog inputs have a large  
common mode voltage or even some noise present along  
with the valid analog signal.  
The zero of the A/D does not require adjustment. If the  
minimum analog input voltage value, V  
is not ground,  
IN MIN  
a zero offset can be done. The converter can be made to  
output 00000000 digital code for this minimum input  
voltage by biasing any V – input at this V  
value.  
IN  
IN MIN  
This utilizes the differential mode operation of the A/D.  
The zero error of the A/D converter relates to the location  
of the first riser of the transfer function and can be  
The differential input of these converters reduces the effects  
of common mode input noise. Thus, if a common mode  
voltage is present on both “+” and “–” inputs, such as 60Hz,  
the converter will reject this common mode voltage since it  
only converts the difference between “+” and “–” inputs.  
measured by grounding the V – input and applying a  
IN  
small magnitude positive voltage to the V + input. Zero  
IN  
error is the difference between the actual DC input  
voltage which is necessary to just cause an output digital  
code transition from 00000000 to 00000001 and the ideal  
1/2 LSB value (1/2 LSB = 9.8mV for V  
= 5.000V ).  
REF  
DC  
The ML2280 and ML2283 have a true sample and hold  
circuit which samples both “+” and “–” inputs  
FULL-SCALE ADJUSTMENT  
simultaneously. This simultaneous sampling with a true S/H  
will give common mode rejection and AC linearity  
performance that is superior to devices where the two input  
terminals are not sampled at the same instant and where  
true sample and hold capability does not exist. Thus, these  
A/D converters can reject AC common mode signals from  
DC-50kHz as well as maintain linearity for signals from DC-  
50kHz.  
The full-scale adjustment can be made by applying a  
differential input voltage which is 1-1/2 LSB down from  
the desired analog full-scale voltage range and then  
adjusting the magnitude of the V  
digital output code which is just changing from 11111110  
to 11111111.  
input or V for a  
REF  
CC  
ADJUSTMENT FOR AN ARBITRARY ANALOG  
INPUT VOLTAGE RANGE  
The signal at the analog input is sampled during the interval  
when the sampling switch is closed prior to conversion start.  
The sampling window (S/H acquisition time) is 1/2 CLK  
period wide and occurs 1/2 CLK period before DO goes  
from high impedance to active low state. When the  
sampling switch closes at the start of the S/H acquisition  
time, 8pF of capacitance is thrown onto the analog input. 1/  
2 CLK period later, the sampling switch is opened and the  
signal present at the analog input is stored. Any error on the  
analog input at the end of the S/H acquisition time will  
cause additional conversion error. Care should be taken to  
allow adequate charging or settling time from the source.  
If more charging or settling time is needed to reduce these  
analog input errors, a longer CLK period can be used.  
If the analog zero voltage of the A/D is shifted away from  
ground (for example, to accommodate an analog input  
signal which does not go to ground), this new zero  
reference should be properly adjusted first. A V + voltage  
IN  
which equals this desired zero reference plus 1/2 LSB  
(where the LSB is calculated for the desired analog span,  
1 LSB = analog span/256) is applied to selected “+” input  
and the zero reference voltage at the corresponding “–”  
input should then be adjusted to just obtain the 00000000  
to 00000001 code transition.  
The full-scale adjustment should be made by forcing a  
voltage to the V + input which is given be:  
IN  
For latchup immunity each analog input has dual diodes to  
the supply rails, and a minimum of ±25mA (±100mA  
typically) can be injected into each analog input without  
causing latchup.  
(VMAX VMIN  
)
VIN + fs adjust = VMAX 1.5×  
256  
where  
V
V
= high end of the analog input range  
MAX  
MIN  
= low end (offset zero) of the analog range  
The V  
or V voltage is then adjusted to provide a  
REF  
CC  
code change from 11111110 to 11111111.  
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