ML2280, ML2283
When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of 1/2
clock period is used for sample & hold settling through the
selected MUX channels. The SAR status output goes high
at this time to signal that a conversion is now in progress
and the DI input is ignored.
REFERENCE
The ML2280 and ML2283 are intended primarily for use in
circuits requiring absolute accuracy. In this type of system,
the analog inputs vary between very specific voltage limits
and the reference voltage for the A/D converter must remain
stable with time and temperature. For ratiometric
applications, see the ML2281 and ML2284 which have a
V
REF
input that can be tied to V
.
CC
The DO output comes out of High impedance and
provides a leading zero for this one clock period.
The voltage applied to the V
pin defines the voltage
REF/2
span of the analog input (the difference between VIN+ and
When the conversion begins, the output of the
VI ) over which the 256 possible output codes apply. A
N–
comparator, which indicates whether the analog input is
greater than or less than each successive voltage from the
internal DAC, appears at the DO output on each falling
edge of the clock. This data is the result of the conversion
being shifted out (with MSB coming first) and can be read
by external logic or µP immediately.
full-scale conversion (an all 1s output code) will result when
the voltage difference between a selected “+”input and “–”
input is approximately twice the voltage at the V
pin.
REF/2
This internal gain of 2 from the applied reference to the full-
scale input voltage allows biasing a low voltage reference
diode from the 5V converter supply. To accommodate a
DC
5V input span, only a 2.5V reference is required. The output
code changes in accordance with the following equation:
After 8 clock periods, the conversion is completed. The SAR
status line returns low to indicate this 1/2 clock cycle later.
V (+) − V (−)
IN
IN
Output Code = 256
The serial data is always shifted out MSB first during the
conversion. After the conversion has been completed, the
data can be shifted out a second time with LSB first. The
2280 data is shifted out only once, MSB first.
2(VREF / 2
)
where the output code is the decimal equivalent of the 8-bit
binary output (ranging from 0 to 255) and the term V
the voltage to ground.
is
REF/2
All internal registers are cleared when the CS input is
high. If another conversion is desired, CS must make a
high to low transition followed by address information.
The V
pin is the center point of a two resistor divider
REF/2
(each resistor is 10kW) connected from V to ground. Total
CC
ladder input resistance is the parallel combination of these
two equal resist. As show in Figure 8, a reference diode
requiring an external biasing resistor if its current
requirements meet the indicated level.
The DI input and DO output can be tied together and
controlled through a bidirectional µP I/O bit with one
connection. This is possible because the DI input is only
latched in during the MUX addressing interval while the
DO output is still in the high impedance state.
The minimum value of V
can be quite small (See
REF/2
Typical Performance Curves) to allow direct conversions of
transducer outputs providing less than a 5V output span.
Particular care must be taken with regard to noise pickup,
circuit layout and system error voltage sources when
operating with a reduced span due to the increased
sensitivity of the converter (1LSB equals V
).
REF/256
V
5V
CC
V
CC
5V
10kΩ
10kΩ
+
V
REF/2
ML2280
ML2283
ML2280
ML2283
V
REF/2
2.5V
I
Z
10kΩ
10kΩ
V
Z
1.2V
GND
GND
–
V
2.4V
V
5.0V
FULL-SCALE
FULL-SCALE
V
– V
V
CC/2
Z
CC
2
NOTE: NO EXTERNAL BIASING RESISTOR NEENED IF: V
<
AND I min. <
Z
Z
5kΩ
Figure 8. Reference Biasing
11
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
