ML2252, ML2259
IntermodulationDistortion
The signal OE drives the data bus, DB0–DB7, into the
high impedance state when held low. This allows the
ML2252 and ML2259 to be tied directly to a µP system
bus without any latches or buffers.
With inputs consisting of sine waves at two frequencies,
f and f , any active device with nonlinearities will
A
B
create distortion products, of order (m + n), at sum and
difference frequencies of mf + nf , where m, n = 0, 1, 2,
A
B
1.7.1 Restart During Conversion
3,... . Intermodulation terms are those for which m or n is
not equal to zero. The (IMD) intermodulation distortion
If the A/D is restarted (start goes low and returns high)
during a convesion, the converter is reset and a new
conversion is started. The output data latch is not updated
if the conversion in process is not allowed to be
completed. EOC will remain low and the output data
latch is not updated.
specification includes the second order terms (f + f ) and
A
A
B
B
(f – f ) and the third order terms (2f + f ), (2f – f ),
A
B
A
B
(f + 2f ) and (f – 2f ) only.
A
B
A
B
1.7 DIGITAL INTERFACE
The analog inputs are selected by the digital addresses,
ADDR0–ADDR2, and latched on the rising edge of ALE.
This is described in the Multiplexer Addressing section.
1.7.2ContinuousConversions
In the free-running, continuous conversion mode, the start
input is tied to the (figure 7) EOC output. An initialization
pulse, following power-up, of mementarily forcing a logic
high level is required to guarantee operation.
A conversion is initiated by the rising edge of a START
pulse. As long as this pulse is high, the internal logic is
reset.
The sampling interval starts with the following CLK rising
edge after a START falling edge and ends on the falling
edge of CLK. The conversion starts and EOC goes low. The
sampling clock is at least one half CLK period wide. Each
bit conversion in the successive approximation process
takes 1 CLK period. On the rising edge of the ninth CLK
pulse, the digital output of the conversion is updated on
the outputs DB0–DB7 and EOC goes high indicating the
conversion is done and data on DB0–DB7 is valid.
ML2252
ML2259
V
CC
START
START
EOC
One feature of the ML2252 and ML2259 is that the data is
double buffered. This means that the outputs DB0–DB7
will stay valid until updated at the end of the next
conversion and will not become invalid when the next
conversion starts. This facilitates interfacing with external
logic of µP.
Figure 7. Continuous Conversion Mode
2.0 TYPICAL APPLICATIONS
V
CC
(5V
)
DC
4k
–
15V
V
DC
CC
+
+V
REF
V
CC
1k
+
FS
ADJ
+
+
–
0.85V
CC
600Ω
ANALOG
IN
10µF
V
CC
ML2252
ML2259
24k
10µF
ML2252
ML2259
XDR
CH
–15V
DC
20k
–
GND
–V
REF
1k
3k
+
0.15V
ZERO ADJ
CC
Figure 8. Protecting the Input
Figure 9. Operating with Ratiometric Transducers 15% of
- V - 85% of V
V
CC
XDR
CC
10
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
