ML2111
FUNCTIONAL DESCRIPTION
POWER SUPPLIES
f /f RATIO
CLK 0
The analog (V ) and digital (V ) supply pins, in most
The ML2111 is a sampled data filter and approximates
continuous time filters. The filter deviates from its ideal
A+
D+
cases, are tied together and bypassed to AGND with
100nF and 10nF disk ceramic capacitors. The supply pins
can be bypassed separately if a high level of digital noise
exists. These pins are internally connected by the IC
substrate and should be biased from the same DC source.
The ML2111 operates from either a single supply from 4V
to 12V, or with dual supplies at ±2V to ±6V.
continuous filter model when the (f /f ) ratio decreases
CLK 0
and when the Qs are low.
f ´ Q PRODUCT RATIO
0
The f ´ Q product of the ML2111 depends on the clock
0
frequency and the mode of operation. The f ´ Q product
0
CLOCK INPUT PINS AND LEVEL SHIFT
is mainly limited by the desired f and Q accuracy for
0
clock frequencies below 1MHz in mode 1 and its
derivatives. If the clock to center frequency ratio is
With dual supplies equal to or higher than ±4.0V, the LSh
pin can be connected to the same potential as either the
lowered below 50:1, the f ´ Q product can be further
0
AGND or the V - pin. With single supply operation the
increased for the same clock frequency and for the same
Q value.
A
negative supply pins and LSh pin should be tied to the
system ground. The AGND pin should be biased half way
between V and V . Under these conditions the clock
Mode 3, (Figure 23) and the modes of operation where R4
is finite, are "slower" than the basic mode 1. The resistor
R4 places the input op amp inside the resonant loop. The
finite GBW of this op amp creates an additional phase
shift and enhances the Q value at high clock frequencies.
A+
A-
levels are TTL or CMOS compatible. Both input clock
pins share the same level shift pin.
50/100/HOLD
Tying the 50/100/HOLD pin to the V and V pins
OUTPUTNOISE
A+
D+
makes the filter operate in the 50:1 mode. Tying the pin
half way between V and V makes the filter operate in
The wideband RMS noise on the outputs of the ML2111 is
nearly independent of the clock frequency, provided that
the clock itself does not become part of the noise. Noise
at the BP and LP outputs increases for high values of Q.
A+
A-
the 100:1 mode. The input range for 50/100/HOLD is
either 2.5V ±0.5V with a total power supply range of 5V,
or 5V ±0.5V with a total power supply range of 10V.
When 50/100/HOLD is tied to the negative power supply
input, the filter operation is stopped and the bandpass and
lowpass outputs act as a sample/hold circuit which holds
the last sample.
FILTER FUNCTION DEFINITIONS
Each filter of the ML2111, along with external resistors
and a clock, approximates second order filter functions.
These are tabulated below in the frequency domain.
S1 & S1
A
B
These voltage signal input pins should be driven by a
source impedance of less than 5kW. The S and S pins
can be used to feedforward the input signal for allpass
filter configurations (see modes 4 & 5) or to alter the
clock-to-center-frequency ratio (f /f ) of the filter (see
modes 1b, 1c, 2a, & 2b). When these pins are not used
they should be tied to the AGND pin.
1. Bandpass function: available at the bandpass output
1A
1B
pins (BP , BP ), Figure 12.
A
B
s w0
CLK 0
Q
G(s) = HOBP
s w
ꢀ ꢃ
0
(1)
s2 +
+ w
0
2
ꢂ ꢅ
ꢁ
Q
ꢄ
S
A/B
where:
When S
is high, the S2 negative input of the voltage
A/B
summing device is tied to the lowpass output. When the
H
= Gain at w = w
OBP 0
S
pin is connected to the negative supply, the S2 input
A/B
switches to ground.
f = w /2p. The center frequency of the complex pole
0 0
pair is f . It is measured as the peak frequency of the
0
AGND
bandpass output.
AGND is connected to the system ground for dual supply
operation. When operating with a single positive supply
the analog ground pin should be biased half way between
Q = the Quality factor of the complex pole pair. It is
the ratio of f to the -3dB bandwidth of the 2nd order
0
bandpass function. The Q is always measured at the
filter BP output.
V
and V , and bypassed with a 100nF capacitor. The
A+
A-
positive inputs of the internal op amps and the reference
point of the internal switches are connected to the AGND
pin.
12