ML2111
PIN CONFIGURATION
ML2111
20-Pin PDIP (P20)
20-Pin SOIC (S20)
LP
BP
1
2
3
4
5
6
7
8
9
20 LP
B
A
A
19 BP
B
N/AP/HP
INV
18 N/AP/HP
B
A
17 INV
A
B
S1
16 S1
B
A
S
15 AGND
A/B
V
14
13
V
V
A+
D+
A-
V
D-
LSh
12 50/100/HOLD
11 CLK
CLK 10
A
B
TOP VIEW
PIN DESCRIPTION
PIN NAME
FUNCTION
PIN NAME
FUNCTION
1
2
3
LP
Lowpass output for biquad A.
11
12
CLK
Clock input for biquad B.
A
B
BP
Bandpass output for biquad A.
50/100/HOLDInput pin to control the clock-to-
center-frequency ratio of 50:1 or
100:1, or to stop the clock to hold the
last sample of the bandpass or lowpass
outputs.
A
N/AP/HP
Notch/allpass/highpass output for
biquad A.
A
4
5
INV
Inverting input of the summing op amp
for biquad A.
A
13
14
15
16
V
V
Negative digital supply.
Negative analog supply.
Analog ground.
D-
S1
Auxiliary signal input pin used in
modes 1a, 1d, 4, 5, and 6b.
A
A-
AGND
S1
6
7
8
9
S
Controls S2 input function.
Positive analog supply.
Positive digital supply.
A/B
Auxiliary signal input pin used in
modes 1a, 1d, 4, 5, and 6b.
B
V
V
A+
17
18
INV
Inverting input of the summing op amp
for biquad B.
D+
B
LSh
Reference point for clock input levels.
Logic threshold typically 1.4V above
LSh voltage.
N/AP/HP
Notch/allpass/highpass output for
biquad B.
B
10
CLK
Clock input for biquad A.
19
20
BP
Bandpass output for biquad B.
Lowpass output for biquad B.
A
B
LP
B
2
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
