ML2037
FUNCTIONAL DESCRIPTION
The ML2037 is composed of a programmable frequency
generator, a sine wave generator, a crystal oscillator, and
a digital interface. The functional block diagram is shown
in Figure 1.
The output filter smooths the analog output by removing
the high frequency sampling components. The resultant
voltage on V
is a sinusoid with the second and third
OUT
harmonic distortion components at least 40dB below the
fundamental.
PROGRAMMABLE FREQUENCY GENERATOR
The ML2037 has a 2-bit (G1, G0) digital gain control.
With the gain input equal to logic 00, the sine wave
The programmable frequency generator produces a digital
output whose frequency is determined by a 16-bit digital
word.
amplitude is equal to 0.5V . Incrementing the gain
P-P
control input increases the output amplitude in 0.5V steps
to a maximum of 2.0V . The output amplitude is
P-P
The frequency generator is composed of a phase
accurate to within ±0.5dB over the frequency range.
accumulator which is clocked at ½f
. The value
CLK IN
stored in the data latch is added to the phase accumulator
every two cycles of CLK IN. The frequency of the analog
output is equal to the rate at which the accumulator
overflows and is given by the following equation:
G1
0
0
1
1
G0
0
1
0
1
P–P OUTPUTAMPLITUDE
.5V
1.0V
1.5V
2.0V
fCLKIN
0
D15 D0
5DEC
fOUT
(1)
222
Where (D15–D0) is the decimal value of the
programming word.
The analog section is designed to operate over a
frequency range of DC to 500kHz and is capable of
driving 1kW, 50pF loads at the maximum amplitude of
The frequency resolution and the minimum frequency are
the same and can be calculated using:
2.0V . The sine wave output is typically centered about
P-P
a 2.5V DC level, so for a 2V sine wave, the output will
P-P
swing from 1.5V to 3.5V.
fCLKIN
222
fMIN
When f
(2)
CRYSTAL OSCILLATOR
The crystal oscillator generates an accurate reference
clock for the programmable frequency generator. The
internal clock can be generated with a crystal or external
clock.
= 25MHz, Df
= 5.96Hz (±2.98Hz).
CLK IN
MIN
Lower output frequencies are obtained by using a lower
clock frequency.
The maximum frequency output can be easily calculated
with the following equation:
If a crystal is used, it must be placed between CLK IN and
DGND. An on-chip oscillator will then generate the
internal clock. No other external components are
required. The crystal should be a parallel resonant type
with a frequency between 5MHz to 25.6MHz. It should
be placed physically as close as possible to CLK IN and
DGND, to minimize trace lengths.
fCLKIN
26
fOUT(MAX)
When f
(3)
= 25MHz, f
= 391kHz. Higher
CLK IN
OUT(MAX)
frequencies, up to 500kHz, are obtained by using an
The crystal must have the following characteristics:
• Parallel resonant type
external clock, where 25MHz < f
< 32MHz.
CLK IN
Due to the phase quantization nature of the frequency
generator, spurious tones can be present in the output in
the range of –50dB relative to fundamental. The energy
from these tones is included in the signal to noise +
distortion specification (SND) given in the electrical
table. The frequency of these tones can be very close to
the fundamental, and it is not practical to filter them out.
• Frequency: 5MHz to 25.6MHz
• Maximum ESR: 120W @ 5 to 10MHz, 80W @10 to
15MHz, and 50W @ 15 to 25.6MHz
• Drive level: 500µW
SINEWAVE GENERATOR
• Typical load capacitance: 18 - 20pF
• Maximum case capacitance: 7pF
The sinewave generator is composed of a sine lookup
table, an 8-bit DAC, an output smoothing filter, and an
amplifier. The sine lookup table is addressed by the phase
accumulator. The DAC is driven by the output of the table
and generates a staircase representation of a sine wave.
The frequency of oscillation will be a function of the
crystal parameters and board capacitance. In general,
5
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
