ML2036
PDN–INH
MODE
PDN–INH
PIN
DATA IN
SHIFT REG.
LATI
SINE WAVE OUTPUT
(1)
PDN
VI1, Logic "0"
X
X
VOUT = 0V
(10kW to AGND)
Inhibit
VI2, Inhibit State
Voltage, VSS to
VSS + 0.5V
All 0‘s
Logic "1"
Logic "1"
VOUT goes to approximately VOS
at the next VOS crossing
(See Figure 6)
(1)
PDN
VI3, Logic "1"
All 0‘s
VOUT = 0V
(10kW to AGND)
Note 1: In the power down mode, the oscillator, CLK OUT 1 and CLK OUT 2, shift register, and data latch are all functional.
Table 1. Three Level P -INH Functions.
DN
V
V
POWER DOWN MODE
OS
0V
V
X
INHIBIT MODE
OS
V
256
f
CLK
2048
PEAK
, FOR f
≤
OUT
|V | =
X
0 V
V
PEAK
256
8 π f
π
512
OUT
+ V
SIN
PEAK
+
|V | ≤
X
f
CLK
f
CLK
FOR f
>
OUT
2048
SCK
SID
0
1 2 3 4 5 6 7 8 9 10 11 12 131415
LATI
Figure 6. Power Down and Inhibit Mode Waveforms.
9
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
