ML2036
PIN CONFIGURATION
ML2036
16-Pin Wide SOIC (S16W)
ML2036
14-Pin PDIP (P14)
V
1
2
3
4
5
6
7
14 CLK IN
13 GAIN
12 DGND
11 AGND
SS
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK IN
GAIN
NC
P
-INH
V
DN
SS
PDN-INH
CLK OUT 1
CLK OUT 2
SCK
CLK OUT 1
CLK OUT 2
SCK
DGND
AGND
10
9
V
V
V
OUT
REF
CC
V
V
V
OUT
REF
CC
SID
SID
LATI
LATI
8
TOP VIEW
TOP VIEW
PIN DESCRIPTION (Pin Number in Parentheses is for SOIC Version)
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1 (2)
V
Negative supply (-5V).
8 (9)
V
CC
Positive supply (5V).
SS
2 (3)
3 (4)
4 (5)
5 (6)
P
-INH
Three level input which controls
the inhibit and power down
9 (10)
V
Reference input. The voltage on
this pin determines the peak-to-
DN
REF
modes. Current source pull-up to
peak swing ofV
. V
can be
OUT
REF
V
.
tied toV
.
CC
CC
CLK OUT 1
CLK OUT 2
SCK
Digital clock output from the
internal clock generator that can
10 (11) V
Analog output.
OUT
drive other devices at f
CLK IN
=
=
11 (12) AGND
12 (13) DGND
13 (15) GAIN
14 (16) CLK IN
Analog ground. All analog inputs
and outputs are referenced to this
point.
CLK OUT 1
f
/2.
Digital clock output from the
internal clock generator that can
Digital ground. All digital inputs
and outputs are referenced to this
point.
drive other devices at f
CLK IN
CLK OUT 2
f
/8.
Serial clock. Digital input which
clocks in serial data on its rising
edges.
SetsV
peak amplitude toV
OUT REF
or V /2. Current source pull-
REF
down to DGND.
6 (7)
7 (8)
SID
Serial input data which programs
the frequency ofV
Clock input. The internal clock can
be generated by tying a 3 to
12MHz crystal from this pin to
DGND, or by applying a digital
clock signal directly to the pin.
.
OUT
LATI
Digital input which latches serial
data into the internal data latch on
falling edges.
2
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
