ML2036
FUNCTIONAL DESCRIPTION (Continued)
The crystal must have the following characteristics:
1. Parallel resonant type
INHIBIT AND POWER DOWN MODES
The ML2036 has an inhibit mode and a power down
mode which are controlled by the three-level P –INH
DN
2. Frequency: 3MHz to 12.4MHz
input as described in Table 1. If a logic "1", (V ) is applied
I3
to the P –INH pin, the power down mode is entered by
DN
3. Maximum equivalent series resistance of 15W at a
drive levels of 1µW to 200µW, and 30W at drive levels
of 10nW to 1µW
entering all zeros in the shift register and applying a logic
"1" to LATI and holding it high. A zero data detect circuit
detects when all bits in the shift register are zeros. In this
state, the power consumption is reduced to 11.5mW max,
4. Typical load capacitance: 18pF
5. Maximum case capacitance: 7pF
and V
goes to 0V as shown in Figure 6 and appears as
OUT
10kW to AGND. CLK IN can be left active or removed
during power down mode. Also, the ML2036 can be
placed in the power down mode by applying a logic “0”
The frequency of oscillation will be a function of the
crystal parameters and PC board capacitance. Crystals that
meet these requirements at 12.352000MHz are M-tron
3709-010 12.352 for 0ºC to 70ºC and 3709-020 12.352
for -40ºC to 85ºC operation.
to the P –INH pin, regardless of the contents of the shift
DN
register and the state of LATI.
If V to V + 0.5V (V ) is applied to the P –INH pin,
SS
SS
I2
DN
the inhibit mode is entered by shifting all zeros into the
shift register and applying a logic “1” to the LATI pin.
The ML2036 has two clock outputs that can be used to
drive other external devices. The CLK OUT 1 output is a
buffered output from the oscillator divided by 2. The
CLK OUT 2 output is a buffered output from the oscillator
divided by 8.
Once the inhibit mode is entered V
will complete the
OUT
last half cycle of the sinewave and then be held at
approximately V , such that no voltage step occurs, as
OS
shown in Figure 6.
POWER SUPPLIES
SERIAL DIGITAL INTERFACE
The analog circuits in ML2036 are powered from V to
CC
The digital interface consists of a shift register and data
latch. The serial 16-bit data word on SID is clocked into a
16-bit shift register on rising edges of the serial shift clock,
SCK. The LSB should be shifted in first and the MSB last as
shown in Figure 4. The data that has been shifted into the
shift register is loaded into a 16-bit data latch on the falling
edge of LATI. To insure that true data is loaded into the
data latch from the shift register, LATI falling edge should
occur when SCK is low, as shown in figure 1. LATI should
be low while shifting data into the shift register to avoid
inadvertently entering the power down mode. Note that all
data is entered and latched on the edges, not levels, of
SCK and LATI.
V
and are referenced to AGND. The digital circuits in the
SS
device are powered from V to DGND. It is
CC
recommended that AGND and DGND be connected
together close to the device, and have a good connection
back to the power source.
It is recommended that the power supplies to the device
should be bypassed by placing decoupling capacitors from
V
to AGND and V to AGND as physically close to the
CC
SS
device as possible.
8
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
