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SY100S838ZCTR 参数 Datasheet PDF下载

SY100S838ZCTR图片预览
型号: SY100S838ZCTR
PDF下载: 下载PDF文件 查看货源
内容描述: (±1 , ± 2/3)或( ±2 , ± 4/6)时钟发生芯片 [(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHIP]
分类和应用: 时钟
文件页数/大小: 4 页 / 76 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
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(
÷
1,
÷
2/3) OR (
÷
2,
÷
4/6)
CLOCK GENERATION CHIP
ClockWorks™
SY100S838
SY100S838L
FEATURES
s
3.3V and 5V power supply options
s
50ps output-to-output skew
s
Synchronous enable/disable
s
Master Reset for synchronization
s
Internal 75K
input pull-down resistors
s
Available in 20-pin SOIC package
DESCRIPTION
The SY100S838/L is a low skew (÷1,
÷2/3)
or (÷2,
÷4/
6) clock generation chip designed explicitly for low skew
clock generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the V
BB
output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the V
BB
output should be connected to the CLK
input and bypassed to ground via a 0.01µF capacitor.
The V
BB
output is designed to act as the switching
reference for the input of the SY100S838/L under single-
ended input conditions. As a result, this pin can only
source/sink up to 0.5mA of current.
The Function Select (F
SEL
) input is used to determine
what clock generation chip function is. When FS
EL
input
is LOW, SY100S838/L functions as a divide by 2 and by
4/6 clock generation chip. However, if FS
EL
input is HIGH,
it functions as a divide by 1 and by 2/3 clock chip.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple SY100S838/Ls in a system.
PIN CONFIGURATION
V
CC
20
Q
0
19
Q
0
18
Q
1
17
Q
1
16
Q
2
15
Q
2
14
Q
3
13
Q
3
12
V
EE
11
TOP VIEW
SOIC
Z20-1
1
V
CC
2
EN
3
4
5
CLK
6
V
BB
7
MR
8
V
CC
9
NC
10
F
SEL
DIVSEL CLK
TRUTH TABLE
CLK
Z
ZZ
X
EN
L
H
X
MR
L
L
H
Function
Divide
Hold Q
0–3
Reset Q
0–3
NOTES:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
PIN NAMES
Pin
CLK
Function
Differential Clock Inputs
Function Select Input
Synchronous Enable
Master Reset
Reference Output
Differential
÷1
or
÷2
Outputs
Differential
÷2/3
or
÷4/6
Outputs
Frequency Select Input
Rev.: E
Amendment: /1
F
SEL
L
L
H
H
DIVSEL
L
H
L
H
Q
0,
Q
1
OUTPUTS
Divide by 2
Divide by 2
Divide by 1
Divide by 1
Q
2,
Q
3
OUTPUTS
Divide by 4
Divide by 6
Divide by 2
Divide by 3
F
SEL
EN
MR
V
BB
Q
0,
Q
1
Q
2,
Q
3
DIVSEL
1
Issue Date: August, 1998