Micrel, Inc.
MICRF002/RF022
CAGC Pin
driver is recommended for driving high-capacitance loads.
VDDBB
REFOSC Pin
VDDBB
Active
Bias
1.5µA
67.5µA
200k
Compa-
rator
REFOSC
250
30pF
CAGC
30pF
30µA
VSSBB
VSSBB
Timout
15µA
675µA
Figure 5. REFOSC Pin
The REFOSC input circuit is shown in Figure 5. Input
impedance is high (200kΩ). This is a Colpitts oscillator with
internal 30pF capacitors. This input is intended to work with
standard ceramic resonators connected from this pin to the
VSSBB pin, although a crystal may be used when greater
frequency accuracy is required. The nominal dc bias
voltage on this pin is 1.4V.
VSSBB
Figure 3. CAGC Pin
Figure 3 illustrates the CAGC pin interface circuit. The AGC
control voltage is developed as an integrated current into a
capacitor CAGC. The attack current is nominally 15µA, while
the decay current is a 1/10th scaling of this, nominally
1.5µA, making the attack/decay time constant ratio a fixed
10:1. Signal gain of the RF/IF strip inside the IC diminishes
as the voltage at CAGC decreases. Modification of the
attack/decay ratio is possible by adding resistance from the
SEL0, SEL1, SWEN, and SHUT Pins
VDDBB
Q1
C
AGC pin to either VDDBB or VSSBB, as desired.
Both the push and pull current sources are disabled during
shutdown, which maintains the voltage across CAGC, and
improves recovery time in duty-cycled applications. To
further improve duty-cycle recovery, both push and pull
currents are increased by 45 times for approximately 10ms
after release of the SHUT pin. This allows rapid recovery of
any voltage droop on CAGC while in shutdown.
Q2
VSSBB
to Internal
Circuits
SHUT
Q4
SEL0,
SEL1,
SWEN
Q3
VSSBB
Figure 6a. SEL0, SEL1, SWEN Pins
DO and WAKEB Pins
VDDBB
VDDBB
10µA
Q1
Q2
Compa-
rator
to Internal
Circuits
VSSBB
SHUT
DO
Q3
VSSBB
10µA
Figure 6b. SHUT Pin
VSSBB
Control input circuitry is shown in Figures 6a and 6b. The
standard input is a logic inverter constructed with minimum
geometry MOSFETs (Q2, Q3). P-channel MOSFET Q1 is
a large channel length device which functions essentially
as a “weak” pullup to VDDBB. Typical pull-up current is 5µA,
leading to an impedance to the VDDBB supply of typically
1MΩ.
Figure 4. DO and WAKEB Pins
The output stage for DO (digital output) and WAKEB
(wakeup output) is shown in Figure 4. The output is a 10µA
push and 10µA pull switched-current stage. This output
stage is capable of driving CMOS loads. An external buffer-
M9999-070808
July 2008
13
MICREL [ MICREL SEMICONDUCTOR ]
