Micrel, Inc.
MIC3003GFL
Electrical Characteristics
Symbol
tOFF
tON
tINIT
tINIT2
tFAULT
tRESET
tLOSS_ON
tLOSS_OFF
tDATA
tPROP_IN
tPROP_OUT
Parameter
TXDISABLE Assert Time
TXDISABLE De-assert Time
Initialization Time
Condition
From input asserted to optical output
at 10% of nominal, C
COMP
= 10nF.
From input de-asserted to optical output
at 90% of nominal, C
COMP
= 10nF.
From power on or transmitter enabled to
optical output at 90% of nominal and
TX_FAULT de-asserted. Note 10.
From power on to APC loop-enabled.
From fault condition to TXFAULT
assertion. Note 10.
Length of time TXDISABLE must be
asserted to reset fault condition.
From loss of signal to RXLOS asserted.
From signal acquisition to LOS
de-asserted.
From power on to valid analog
parameter data available. Note 10
Time from input change to
corresponding internal register bit set or
cleared. Note 10.
From an internal register bit set or
cleared to corresponding output change.
Note 10.
Note 10.
0.5
10
95
100
400
1
Min
Typ
Max
Units
µs
ms
ms
Control and Status I/O Timing, TXFAULT, TXDISABLE, RS0, RRSOUT, and RXLOS
10
1
300
Power-on Initialization Time
TXFAULT Assert Time
Fault Reset Time
RXLOS Assert Time
RXLOS De-assert Time
Analog Parameter Data Ready
TXFAULT, TXDISABLE, RXLOS,
RS0, RS1 Input Propagation Time
TXFAULT, TRSOUT, TRRSOUT,
/INT, QGPO Output Propagation
Time
Fault Suppression Timer Clock
Period
Accuracy
Glitch Rejection
Saturation Detection Threshold
200
95
ms
µs
µs
µs
µs
ms
µs
1
µs
Fault Comparators
FLTTMR
0.475
-3
Maximum length pulse that will not
cause output to change state. Note 10.
High level
Low level
4.5
95
5
0.525
+3
ms
%/fs
µs
%VDDA
%VDDA
tREJECT
VSAT
Power-On Hour Meter
Timebase Accuracy
Resolution
0°C
≤
T
A
≤
+70°, Note 10.
–40°C
≤
T
A
≤
+105°C
Note 10.
+5
+10
10
-5
-10
%
%
hours
Non-Volatile (FLASH) Memory
t
WR
Write Cycle Time, Note 11
Measured from the SMBus STOP
condition of a one-byte to eight-byte
write transaction. Note 10.
100
10,000
13
ms
NVRAM Data Retention
Endurance
Notes:
10. Guaranteed by design and/or testing of related parameters. Not 100% tested in production.
years
cycles
Maximum permitted number of write
cycles to any single NVRAM location
11. The MIC3003 will not respond to serial bus transactions during an EEPROM write cycle. The host will receive a NACK response during t
WR
.
July 2010
13
M9999-072910-A
hbwhelp@micrel.com
or (408) 955-1690
MICREL [ MICREL SEMICONDUCTOR ]
