Micrel
MIC2589/MIC2595
VTHRESH(PG3) − VTHRESH(PG2)
× CPG
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
CNLD
tPGDLY3−2
=
tNLD = VCNLD
×
IPGTIMER
ICNLD
where VTHRESH(PG3) (1.15V, typical) is the PWRGD3
threshold voltage for PGTIMER. Therefore, power-
good output signal PWRGD2 (/PWRGD2) will be
delayed after the assertion of PWRGD1 (/PWRGD1)
by:
where VCNLD = 1.24V (typ); ICNLD = 25µA (typ); and
CNLD is an external capacitor connected from Pin 6 to
VEE. Once the voltage on CNLD reaches its no-load
threshold voltage, VCNLD, the loop times out and the
controller will shut down until it is reset manually
(MIC2589/MIC2595) or until it performs an auto-retry
operation (MIC2589R/MIC2595R). During start-up, the
no-load detection circuit begins to monitor the load
current and the CNLD pin starts ramping along with
the GATE output. In order to keep the output from
shutting down, tNLD must be long enough to ensure
that the output MOSFET switches on to deliver the
required minimum load-detect current to the output
load before the no-load timer times out.
tPGDLY2-1 (ms) ≅ 14 × CPG(µF)
Power-good output signal PWRGD3 (/PWRGD3)
follows the assertion of PWRGD2 by a delay:
tPGDLY3-2 (ms) ≅ 11.5 × CPG(µF)
For example, for a 10µF value for CPG, power-good
output signal PWRGD2 will be asserted 140ms after
PWRGD1. Power-good signal PWRGD3 will then be
asserted 115ms after PWRGD2 and 255ms after the
assertion of PWRGD1. The relationships between
The Power-Good Output Signals
V
DRAIN, VPGTH, PWRGD1, PWRGD2, and PWRGD3
are shown in Figure 6.
For
the
MIC2589/MIC2595-1
and
MIC2589R/MIC2595R-1, power-good output signal
PWRGD1 will be high impedance when VDRAIN drops
below VPGTH, and will pull-down to the potential at the
Undervoltage/Overvoltage Detection (MIC2589 and
MIC2589R)
The MIC2589 and the MIC2589R have “UV” and “OV”
input pins that can be used to detect input supply rail
DRAIN when VDRAIN is above VPGTH
. For the
MIC2589/95-2 and the MIC2589R/95R-2, power-good
output signal /PWRGD1 will pull down to the potential
of the DRAIN pin when VDRAIN drops below VPGTH and
undervoltage
and
overvoltage
conditions.
Undervoltage lockout prevents the output from
switching on until the supply input is stable and within
tolerance. In a similar fashion, overvoltage shutdown
prevents damage to sensitive circuit components
should the input voltage exceed normal operating
limits. Each of these pins is internally connected to
analog comparators with 20mV of hysteresis. When
the UV pin falls below its VUVL threshold or the OV pin
is above its VOVH threshold, the GATE pin is
immediately pulled low. The GATE pin will be held low
until the UV pin is above its VUVH threshold and the OV
pin is below its VOVL threshold. The circuit’s UV and
OV threshold voltage levels are programmed using
the resistor divider R1, R2, and R3 as shown in the
“Typical Application” circuit and the equations to set
the trip points are shown below. The circuit’s UV
threshold is set to VUV = 37V and the OV threshold is
set at VOV = 72V, values commonly used in Central
Office power distribution applications.
will be high impedance when VDRAIN is above VPGTH
.
Hence, the -1 parts have an active-high PWRGDX
signal and the -2 parts have an active-low /PWRGDX
output. PWRGDX (or /PWRGDX) may be used as an
enable signal for one or more following DC/DC
converter modules or for other system uses as
desired. When used as an enable signal, the time
necessary for the PWRGD (or /PWRGD) signal to
pull-up (when in high impedance state) will depend
upon the load (RC) that is present on this output.
Power-good output signals PWRGD2 (/PWRGD2) and
PWRGD3 (/PWRGD3) follow the assertion of
PWRGD1 (/PWRGD1) with a sequencing delay set by
an external capacitor (CPG) from the controller’s
PGTIMER pin (Pin 2) to VEE. An expression for the
sequencing delay between PWRGD2 and PWRGD1
is given by:
VTHRESH(PG2) × CPG
R1+ R2 + R3
)
tPGDLY2−1
=
VUV = VUVL (typ)×
IPGTIMER
(
R2 + R3
R1+ R2 + R3
R3
)
where VTHRESH(PG2) (= 0.63V, typically) is the
PWRGD2 threshold voltage for PGTIMER and IPGTIMER
(= 45µA, typically) is the internal PGTIMER charge
current. Similarly, an expression for the sequencing
delay between PWRGD3 and PWRGD2 is given by:
(
)
VOV = VOVL (typ)×
Given VUV, VOV, and any one of the resistor values,
the remaining two resistor values can be determined.
A suggested value for R3 is selected to provide
approximately 100µA (or more) of current through the
voltage divider chain at VDD = VUV. This yields the
18
M9999-120505
(408) 955-1690
December 2005
MICREL [ MICREL SEMICONDUCTOR ]
