MIC2589/2595
Micrel
The Power-Good Output Signals
Functional Description
Hot Swap Insertion
For the MIC2589/95-1 and MIC2589R/95R-1, power-good
output signal PWRGD1 will be high impedance when V
DRAIN
When circuit boards are inserted into systems carrying live
supply voltages (“hot swapped”), high inrush currents often
result due to the charging of bulk capacitance that resides
across the circuit board’s supply pins. These current spikes
can cause the system’s supply voltages to temporarily go out
of regulation causing data loss or system lock-up. In more
extreme cases, the transients occurring during a hot swap
event may cause permanent damage to connectors or on-
board components.
drops below V
, and will pull-down to V
when
PGTH
DRAIN
V
is above V
. For the MIC2589/95-2 and the
DRAIN
PGTH
MIC2589R/95R-2, power-good output signal /PWRGD1 will
pull down to the potential of the V
pin when V
DRAIN
DRAIN
and will be high impedance when V
DRAIN
drops below V
is above V
PGTH
. Hence, the -1 parts have an active-high
PGTH
PWRGD signalandthe-2partshaveanactive-low/PWRGD
X
X
output. PWRGD (or /PWRGD ) may be used as an enable
X
X
signal for one or more following DC/DC converter modules or
for other system uses as desired. When used as an enable
signal, the time necessary for the PWRGD (or /PWRGD)
signal to pull-up (when in high impedance state) will depend
upon the load (RC) that is present on this output.
The MIC2589 and the MIC2595 are designed to address
these issues by limiting the maximum current, which is
allowed to flow during hot swap events. This is achieved by
implementing a constant-current loop at turn-on. In addition
to inrush current control, the MIC2589 and the MIC2595
incorporate input voltage supervisory functions and user-
programmable overcurrent protection, thereby providing ro-
bust protection for both the system and the circuit board.
Power-good output signals PWRGD2 (/PWRGD2) and
PWRGD3 (/PWRGD3) follow the assertion of PWRGD1
(/PWRGD1) with a sequencing delay set by an external
capacitor (C ) from the controller’s PGTIMER pin (Pin 2) to
PG
Start-Up Cycle
V
. An expression for the sequencing delay between
EE
PWRGD2 and PWRGD1 is given by:
WhentheinputvoltageistotheICisbetweentheovervoltage
and undervoltage thresholds (MIC2589 and MIC2589R) or is
V
THRESH(PG2) × CPG
greater than V (MIC2595 and MIC2595R), a start cycle is
tPGDLY2−1
where V
=
ON
IPGTIMER
initiated. When the IC is enabled, the GATE pin voltage rises
from 0V with respect to V to approximately 10V above V
.
EE
EE
(= 0.63V, typically) is the PWRGD2
THRESH(PG2)
This 10V gate drive is sufficient to fully enhance commonly
availablepowerMOSFETsforthelowestpossibleDClosses.
threshold voltage for PGTIMER and I
(= 45µA, typi-
PGTIMER
cally) is the internal PGTIMER charge current. Similarly, an
expression for the sequencing delay between PWRGD3 and
PWRGD2 is given by:
Capacitor C
compensates circuitry internal to the IC,
GATE
while R4 minimizes the potential for high frequency parasitic
oscillations from occurring in M1. The drain current of the
MOSFET is regulated to ensure that it never exceeds the
programmed threshold, as described in the “Circuit Breaker
Function” section.
V
– V
× C
PG
(
)
THRESH(PG3)
THRESH(PG2)
t
=
PGDLY3−2
I
PGTIMER
Capacitor C
sets the value of overcurrent detector
where V
(= 1.15V, typically) is the PWRGD3
FILTER
THRESH(PG3)
delay, t , which is the time for which an overcurrent event
threshold voltage for PGTIMER. Therefore, power-good out-
put signal PWRGD2 (/PWRGD2) will be delayed after the
assertion of PWRGD1 (/PWRGD1) by:
FLT
must last to signal a fault condition and to cause an output
latch-off. These devices will be driving a capacitive load in
most applications, so a properly chosen value of C
prevents false-, or nuisance-, tripping at turn-on as well as
providing immunity to noise spikes after the start-up cycle is
complete. The procedure for selecting a value for C
FILTER
t
(ms) 14 × C (µF) ms
PG
PGDLY2-1
Power-good output signal PWRGD3 (/PWRGD3) follows the
assertion of PWRGD2 by a delay:
is
FILTER
t
(ms) 11.5 × C (µF) ms
PG
given in the “Circuit Breaker Function” section.
PGDLY3-2
For example, for a 10µF value for C , power-good output
ResistorR4,inserieswiththepowerMOSFET’sgate,maybe
required in some layouts to minimize the potential for para-
siticoscillationsoccurringinM1. Notethough, thatresistance
in this device of the circuit has a slight destabilizing effect
upon the MIC2589/95’s current regulation loop. If possible,
usehigh-frequencyPCBlayouttechniquesanduseadummy
resistor, such that R4 = 0Ω. If during prototyping an R4 is
required, common values for R4 range between 4.7Ω to 20Ω
for various power MOSFETs.
PG
signal PWRGD2 will be asserted 140ms after PWRGD1.
Power-good signal PWRGD3 will then be asserted 140ms
after PWRGD2 and 255ms after the assertion of PWRGD1.
The relationships between V
, V
, PWRGD1,
DRAIN
PGTH
PWRGD2, and PWRGD3 are shown in Figure 6.
March 2004
11
M9999-031504
MICREL [ MICREL SEMICONDUCTOR ]
