MIC2584/2585
Micrel
Timing Diagrams
GATE1
GATE2
ON
GATE1 ON
GATE2 ON
GATE1 ON
GATE2 OFF
100mV
OFF
ON
GATE1 OFF
GATE2 ON
VOUT1 - VOUT2
ON Pin Asserted
GATE1 OFF
GATE2 OFF
GATE1 ON
GATE2 OFF
100mV
OFF
GATE1 OFF
GATE2 ON
VOUT1 - VOUT2
ON Pin Deasserted
Figure 2. Gate Voltage Window — Tracking Mode
V
TRIPFAST
50mV
(V
CCx
– V
SENSEx
)
t
OCSLOW
V
GATEx
0.5V
0.5V
t
OCFAST
Figure 3. Current Limit Response
ON
V
START
CPOR
t
START
V
OUT[1,2]
V
PG[1/2]
V
POR
PG
[1/2]
t
POR
/POR
Figure 4. Start-Up Cycle Timing
V
OUT1
∆V<0.25V
V
OUT2
Tracking Mode, TRK = V
OUT1
or V
OUT2
V
OUT1
,V
OUT2
(-1) (-2)
V
FB
V
OUT2
,V
OUT1
(-1) (-2)
∆V<0.25V
∆V<0.25V
t
DLY
Sequencing/Tracking Mode, TRK = V
OUT1
or V
OUT2
(-1) - V
OUT2
follows V
OUT1
(-2) - V
OUT1
follows V
OUT2
Figure 5. Sequencing Modes (MIC2585 only)
MIC2584/2585
8
March 2005
MICREL [ MICREL SEMICONDUCTOR ]
