MIC2564A
Symbol
Parameter
Conditions
Min
Typ
Max
Micrel
Units
Serial Interface Timing Requirements
(See Figure 1),
Note 10
t
HD:DAT
t
SU:DAT
t
SU:SLA
t
SU:RST#
t
W
SDA Hold Time
SDA Setup Time
Latch Setup Time
Reset to Data Setup Time
Minimum Pulse Width
RST# before data
clock (t
W:CLK
)
latch (t
W:SLA
)
reset (t
W:RST
)
data (t
W:DA
)
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
Note 9.
Exceeding the absolute maximum rating may damage the device.
The device is not guaranteed to function outside its operating rating.
Devices are ESD sensitive. Handling precautions recommended.
Output enabled into short circuit.
Measurement is from the 50% point of the SLA rising edge.
Measurement is from the Hi-Z- or 0V-state command to the beginning of the slope. Measurement does not apply when device is in current
limit or thermal shutdown.
V
CC3
IN powers all internal logic, bias, and drive circuitry, and is required for operation.
V
PP
and V
CC5
IN are not required for operation.
V
PP
IN must be either high impedance or greater than or approximately equal to the highest voltage V
CC
in the system. For example, if both
3.3V and 5V are connected to the MIC2564A, V
PP
IN must be either 5V, 12V, or high impedance.
75
data before clock
75
50
50
50
100
50
50
ns
ns
ns
ns
ns
ns
ns
ns
Note 10.
Guaranteed by design not production tested.
Serial Control Timing Diagram
t
W:DAT
RST#
t
SU:RST#
SDA
t
SU:DAT
SLA
t
W:CLK
t
HD:DAT
t
SU:SLA
t
W:SLA
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCL
Figure 1. Serial Control Timing Diagram
The MIC2564A uses a three-wire serial interface to control V
CC
and V
PP
outputs for both sections A and B. The three control
lines have thresholds compatible with both 3.3V and 5V logic families. Data (SDA) is clocked in on the rising clock edge. The
clock signal may be continuous or it may halt after all data is clocked in.
September 1999
5
MIC2564A
MICREL [ MICREL SEMICONDUCTOR ]
