Micrel, Inc.
MIC2555
GPIO Interrupt Mask False
Enables interrupts on transition from TRUE to FALSE
1 Æset = 1, Interrupt on TÆF.
set – 1Ch
clr – 1Dh
Set & Clear
1 Æclr = 0, no interrupt.
GPIO_0
GPIO_1
GPIO_2
1
1
1
1
1
1
1
1
rd/s/c
rd/s/c
rd/s/c
rd/s/c
rd/s/c
rd/s/c
rd/s/c
rd/s/c
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
GPIO Interrupt Mask True
Enables interrupts on transition from FALSE to
TRUE.
set – 1Eh
clr – 1Fh
Set & Clear
1 Æset = 1, Interrupt on FÆT.
1 Æclr = 0, no interrupt.
GPIO_0
GPIO_1
GPIO_2
1
1
1
1
1
1
1
1
rd/s/c
rd/s/c
rd/s/c
rd/s/c
rd/s/c
rd/s/c
rd/s/c
rd/s/c
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Note:
.Access type “rd/s/c” denotes a field that can be read, set to 1 or cleared to 0. The register can be read from either of
the Addresses indicated. When writing to the “set” Address, any 1’s that are written cause the associated bit to be set.
When writing to the “clr” (Clear) Address, any 1s that are written cause the associated bit to be cleared.
Example Serial Controller Register Settings
Example
Location
Target register
Condition
Initial state
BIT 7
0
BIT 6
0
BIT 5
1
BIT 4
0
BIT 3
1
BIT 2
0
BIT 1
0
BIT 0
0
Data loaded into ‘set’
register
‘Set’ register
1
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Target register
‘Clear’ register
Target register
Resulting state
Data loaded into
‘Clear’ register
Resulting state
M9999-060805
(408) 955-1690
June 2005
27
MICREL [ MICREL SEMICONDUCTOR ]
