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KSZ8795CLX 参数 Datasheet PDF下载

KSZ8795CLX图片预览
型号: KSZ8795CLX
PDF下载: 下载PDF文件 查看货源
内容描述: [Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces]
分类和应用: 局域网(LAN)标准
文件页数/大小: 132 页 / 1359 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
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KSZ8795CLX  
TABLE 4-24: EEE GLOBAL REGISTERS (CONTINUED)  
Address Name Description  
EEE Global Register 4  
Global EEE Wakeup Error Threshold Control Register  
Mode  
Default  
Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0x0 for the indirect global register,  
Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.  
Offset: 0x38 (Bits[15:8]), 0x39 (Bits[7:0])  
Location: (001 EEE) -> {0x0, offset} -> 0xA0 holds the data.  
15 - 0  
EEEWakeup This value specifies the maximum time allowed for  
Threshold PHY to wake up.  
RO  
0x0201  
If wakeup time is longer than this, EEE wakeup  
error count will be incremented.  
Note: This is EEE standard, don’t change.  
EEE Global Register 5  
Global EEE PCS Diagnostic Control Register  
Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0x0 for the indirect global register,  
Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.  
Offset: 0x3A (Bits[15:8]), 0x3B (Bits[7:0])  
Location: (001 EEE) -> {0x0, offset} -> 0xA0 holds the data.  
15 - 0  
Reserved  
RO  
0x0001  
TABLE 4-25: EEE PORT REGISTERS  
Address Name Description  
EEE Port Register 0  
Port Auto-Negotiation Expansion Status Register  
Mode  
Default  
Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0xn, n = 1-4 for the Indirect Port Register,  
Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.  
Offset: 0x0C (Bits[15:8]), 0x0D (Bits[7:0])  
Location: (001 EEE) -> {0xn, offset} -> 0xA0 holds the data.  
15 - 7  
6
Reserved  
RO  
RO  
9h000  
1
ReceiveNext 1 = Received Next Page storage location is speci-  
Page Loca- fied by bits[6:5]  
tion Able  
0 = Received Next Page storage location is not  
specified by bits[6:5]  
5
4
Received  
1 = Link Partner Next Pages are stored in MIIM  
RO  
1
0
Next Page Register 8h (Additional next page)  
Storage  
Location  
0 = Link Partner Next Pages are stored in MIIM  
Register 5h  
Parallel  
Detection  
Fault  
1 = A fault has been detected via the Parallel  
Detection function.  
0 = A fault has not been detected via the Parallel  
Detection function.  
R/LH  
This bit is cleared after reading.  
3
Link Partner 1 = Link Partner is Next Page abled  
Next Page 0 = Link Partner is not Next Page abled  
Able  
RO  
0
2
1
Next Page 1 = Local Device is Next Page abled  
RO  
1
0
Able  
0 = Local Device is not Next Page abled  
Page  
1 = A New Page has been received  
R/LH  
Received  
0 = A New Page has not been received  
2016 Microchip Technology Inc.  
DS00002112A-page 99  
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