KS8721BL/SL
Micrel
Type
(2)
Ipd/O
Ipu/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enable RMII back-to-back mode at power-up/reset. PD (default) = Disable,
PU = Enable.
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin is also latched as
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
Latched into Register 0h bit 8 during power-up/reset. PD = Half-duplex, PU
(default) = Full-duplex. If Duplex is pulled up during reset, this pin is also latched as
the Duplex support in register 4h.
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
Power-Down Enable. PU (default) = Normal operation, PD = Power-Down mode.
Strapping Options
(1)
Pin Number
6,5,
4,3
25
9
11
21
22
27
Pin Name
PHYAD[4:1]/
RXD[0:3]
PHYAD0/
INT#
PCS_LPBK/
RXDV
ISO/RXER
RMII/COL
RMII_BTB
CRS
SPD100/
No FEF/
LED1
DUPLEX/
LED2
NWAYEN/
LED3
PD#
Description
PHY Address latched at power-up/reset. The default PHY address is 00001.
28
Ipu/O
29
30
Notes:
Ipu/O
Ipu
1. Strap-in is latched during power-up or reset.
2. Ipu = Input w/ internal pull-up.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
See “Reference Circuit” section for pull-up/pull-down and float information.
May 2004
9
M9999-051704
MICREL [ MICREL SEMICONDUCTOR ]
