KS8721B/BT
Micrel
Pin Description
Pin Number
1
2
3
Pin Name
MDIO
MDC
RXD3/
PHYAD1
Type
(Note 1)
I/O
I
Ipd/O
Pin Function
Management Interface (MII) Data I/O: This pin requires an external 10K pull-up
resistor.
Management Interface (MII) Clock Input: This pin is synchronous to the MDIO
data interface
MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK.
When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is
latched as PHYADDR [1] during reset. See
“Strapping Options”
section for
details.
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2]
during reset. See
“Strapping Options”
section for details.
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3]
during reset. See
“Strapping Options”
section for details.
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4]
during reset. See
“Strapping Options”
section for details.
Digital IO 2.5 /3.3V tolerance power supply.
Ground.
MII Receive Data Valid Output: The pull-up/pull-down value is latched as
pcs_lpbk during reset. See
“Strapping Options”
section for details.
MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE
during reset. See
“Strapping Options”
section for details.
Ground.
Digital core 2.5V only power supply.
MII Transmit Error Input.
MII Transmit Clock Output: RMII Reference Clock Input.
MII Transmit Enable Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select
during reset. See
“Strapping Options”
section for details.
Digital IO 2.5/3.3V tolerance power supply.
4
5
6
7
8
9
RXD2/
PHYAD2
RXD1/
PHYAD3
RXD0/
PHYAD4
VDDIO
GND
RXDV/
CRSDV/
PCS_LPBK
RXC
RXER/ISO
GND
VDDC
TXER
TXC/
REFCLK
TXEN
TXD0
TXD1
TXD2
TXD3
COL/RMII
VDDIO
Ipd/O
Ipd/O
Ipd/O
Pwr
GND
Ipd/O
10
11
12
13
14
15
16
17
18
19
20
21
24
Note 1.
O
Ipd/O
GND
Pwr
Ipd
Ipu/O
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd/O
Pwr
Pwr = power supply
GND = ground
I = input
O = output
I/O = bi-directional
Gnd = ground
Ipu = input w/ internal pull-up
Ipd = input w/ internal pull-down
Ipd/O = input w/ internal pull-down during reset, output pin otherwise
Ipu/O = input w/ internal pull-up during reset, output pin otherwise
PU = strap pin pull-up
PD = strap pin pull-down
NC = No connect
KS8721B/BT
6
August 2003
MICREL [ MICREL SEMICONDUCTOR ]
