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KSZ8041NLAMTR 参数 Datasheet PDF下载

KSZ8041NLAMTR图片预览
型号: KSZ8041NLAMTR
PDF下载: 下载PDF文件 查看货源
内容描述: [DATACOM, QCC32, 5 X 5 MM, LEAD FREE, MLF-32]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 54 页 / 664 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
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Micrel, Inc.  
KSZ8041NL/RNL  
Pin Description – KSZ8041NL  
Type(1)  
Pin Number Pin Name  
Pin Function  
1
2
3
4
5
6
7
8
GND  
Gnd  
P
Ground  
VDDPLL_1.8  
VDDA_3.3  
RX-  
1.8V analog VDD  
P
3.3V analog VDD  
I/O  
I/O  
I/O  
I/O  
O
Physical receive or transmit signal (- differential)  
Physical receive or transmit signal (+ differential)  
Physical transmit or receive signal (- differential)  
Physical transmit or receive signal (+ differential)  
Crystal feedback  
RX+  
TX-  
TX+  
XO  
This pin is used only in MII mode when a 25 MHz crystal is used.  
This pin is a no connect if oscillator or external clock source is used, or if RMII mode  
is selected.  
9
XI /  
I
Crystal / Oscillator / External Clock Input  
REFCLK  
MII Mode:  
25MHz +/-50ppm (crystal, oscillator, or external clock)  
50MHz +/-50ppm (oscillator, or external clock only)  
RMII Mode:  
10  
REXT  
I/O  
Set physical transmit output current  
Connect a 6.49KΩ resistor in parallel with a 100pF capacitor to ground on this pin.  
See KSZ8041NL reference schematics.  
11  
12  
13  
MDIO  
MDC  
I/O  
I
Management Interface (MII) Data I/O  
This pin requires an external 4.7KΩ pull-up resistor.  
Management Interface (MII) Clock Input  
This pin is synchronous to the MDIO data interface.  
MII Mode:  
Receive Data Output[3](2)  
/
RXD3 /  
Ipu/O  
PHYAD0  
Config Mode:  
The pull-up/pull-down value is latched as PHYADDR[0] during  
power-up / reset. See “Strapping Options” section for details.  
14  
15  
RXD2 /  
Ipd/O  
Ipd/O  
MII Mode:  
Receive Data Output[2](2)  
/
PHYAD1  
Config Mode:  
The pull-up/pull-down value is latched as PHYADDR[1] during  
power-up / reset. See “Strapping Options” section for details.  
RXD1 /  
MII Mode:  
Receive Data Output[1](2)  
Receive Data Output[1](3)  
/
/
RXD[1] /  
PHYAD2  
RMII Mode:  
Config Mode:  
The pull-up/pull-down value is latched as PHYADDR[2] during  
power-up / reset. See “Strapping Options” section for details.  
16  
RXD0 /  
Ipu/O  
MII Mode:  
Receive Data Output[0](2)  
Receive Data Output[0](3)  
/
/
RXD[0] /  
DUPLEX  
RMII Mode:  
Config Mode:  
Latched as DUPLEX (register 0h, bit 8) during power-up /  
reset. See “Strapping Options” section for details.  
17  
18  
VDDIO_3.3  
RXDV /  
P
3.3V digital VDD  
MII Mode:  
Ipd/O  
Receive Data Valid Output /  
CRSDV /  
CONFIG2  
RMII Mode:  
Config Mode:  
Carrier Sense/Receive Data Valid Output /  
The pull-up/pull-down value is latched as CONFIG2 during  
power-up / reset. See “Strapping Options” section for details.  
19  
RXC  
O
MII Mode:  
Receive Clock Output  
September 2010  
10  
M9999-090910-1.4