DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Ordering Information
(Example shown in red font)
Q
DSC400- 4 3 2 1 x x x x K E 1 T
CLK3 Output Format
0: off
1: LVCMOS
2: LVPECL
3: LVDS
Packing
T: Tape & Reel
Stability
1: ±50ppm
2: ±25ppm
4: HCSL
CLK2 Output Format
1: LVCMOS
2: LVPECL
Temp Range
E: -20ºC to 70ºC
I: -40ºC to 85º
3: LVDS
4: HCSL
Package
K: 20 QFN
CLK1 Output Format
0: off
1: LVCMOS
2: LVPECL
3: LVDS
Frequency Code
Qxxxx is assigned
by factory; see
Table2
4: HCSL
CLK0 Output Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
Factory configuration code assignment of Qxxxx
The DSC400 is meant for customers to define their own frequency requirements at the four
available outputs. The Qxxxx number identifies these specific customer requirements and is
assigned by the factory.
Table 2: Example of how FSB1 and FSB2 are applied and the Qxxxx code assignment
Bank1
FSB1
Qxxxx number
Outputs
CLK0
1 (default)
125 MHz
50 MHz
0
150 MHz
25 MHz
CLK3
Bank2
FSB2
Q0001
Outputs
CLK1
1 (default)
0
156.25 MHz
156.25 MHz
100 MHz
100 MHz
CLK2
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DSC400 Page 4
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