DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
LVPECL Outputs6
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
RL=50Ω
VDD-1.08
-
-
V
VDD-1.55
Pk to Pk Output Swing
Output Transition time4
Rise Time
Single-Ended
800
250
mV
ps
20% to 80%
tR
tF
RL=50Ω
Fall Time
Frequency
f0
Single Frequency
Differential
2.3
48
460
52
MHz
%
Output Duty Cycle
SYM
Supply Current – IO2
IDDio
JPER
Per output at 125MHz
35
38
mA
Period Jitter5
CLK(0:3) = 156.25 MHz
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
2.5
0.25
0.38
1.7
psRMS
Integrated Phase Noise
JPH
psRMS
2
Notes:
5.
6.
Period Jitter includes crosstalk from adjacent output
LVPECL applicable to ext. commercial temperature only
LVPECL: Typical Termination Scheme
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DSC400 Page 6
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