DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
HCSL Outputs
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
RL=50Ω
0.725
-
-
0.1
V
Pk to Pk Output Swing
Output Transition time3
Rise Time
Single-Ended
750
mV
ps
20% to 80%
RL=50Ω, CL= 2pF
tR
tF
200
400
Fall Time
Frequency
f0
Single Frequency
Differential
2.3
48
460
52
MHz
%
Output Duty Cycle
Supply Current – IO2
Period Jitter
SYM
IDDio
JPER
Per output at 125MHz
20
22
mA
2.5
psRMS
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.25
0.37
1.7
Integrated Phase Noise
JPH
psRMS
2
HCSL: Typical Termination Scheme
RS is a series resistor implemented to match the trace impedance. Depending on the board
layout, the value may range from 0 to 30Ω
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DSC400
Page 8
MICREL [ MICREL SEMICONDUCTOR ]
