DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
LVCMOS Outputs
Output Logic Levels
Output logic high
Output logic low
Output Transition time3
Rise Time
VOH
VOL
I=±6mA
0.9xVDD
-
-
V
0.1xVDD
20% to 80%
CL=15pF
tR
tF
1.1
1.3
2
2
ns
Fall Time
All temp range except Auto
Auto temp range
2.3
45
170
100
Frequency
f0
MHz
%
Output Duty Cycle
Supply Current – IO2
Period Jitter
SYM
55
14
IDDio
JPER
Per output at 125MHz, CL=15pF
CLK(0:3) =125MHz
11
3
mA
psRMS
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
0.3
0.38
1.7
Integrated Phase Noise
JPH
psRMS
2
LVCMOS: Typical Termination Scheme
RS is a series resistor implemented to match the trace impedance to that of the clock
output. Depending on the board layout, the value may range from 0 to 27Ω
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DSC400 Page 9
MICREL [ MICREL SEMICONDUCTOR ]
