DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
LVDS Outputs
Output offset Voltage
Delta Offset Voltage
Pk to Pk Output Swing
Output Transition time3
Rise Time
VOS
∆VOS
VPP
R=100Ω Differential
1.125
1.4
50
V
mV
mV
Single-Ended
350
200
20% to 80%
RL=50Ω, CL= 2pF
tR
tF
ps
Fall Time
Frequency
f0
Single Frequency
Differential
2.3
48
460
52
MHz
%
Output Duty Cycle
Supply Current – IO2
Period Jitter
SYM
IDDio
JPER
Per output at 125MHz
9
12
mA
2.5
psRMS
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.28
0.4
1.7
Integrated Phase Noise
JPH
psRMS
2
LVDS: Typical Termination Scheme
If the 100Ω clamping resistor does not exist inside the receiving device, it should be added externally on the
PCB and placed as close as possible to the receiver.
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DSC400
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MICREL [ MICREL SEMICONDUCTOR ]
