Micrel, Inc.
DSC400-0101Q0082
LVCMOS Outputs
Output Logic Levels
Output Logic High
Output Logic Low
VOH
VOL
I = ±6mA
0.9 x VDD
-
V
-
0.1 x VDD
Output Transition Time³
Rise Time
20% to 80%
CL = 15pF
tR
tF
1.1
1.3
2
2
ns
Fall Time
f1
f3
CLK1
CLK3
22.5792
24.576
Frequency
MHz
Output Duty Cycle
Supply Current - IO²
Period Jitter
SYM
Differential
45
55
14
%
IDDio Per output at 125MHz, CL = 15pF
11
3
mA
JPER
CLK(1:4) = 125MHz
psRMS
200kHz to 20MHz @ 156.25MHz
100kHz to 20MHz @ 156.25MHz
12kHz to 20MHz @ 156.25MHz
0.3
0.38
1.7
Integrated Phase Noise
JPH
psRMS
2
LVCMOS Typical Termination Scheme
S
R is a series resistor implemented to match the trace impedance to that of the clock output. Depending on the board layout,
the value may range from 0 to 27Ohms.
LVCMOS Output Waveform
April 20, 2016
3819
6
Revision 1.0
tcghelp@micrel.comor (408) 955-1690
MICREL [ MICREL SEMICONDUCTOR ]
