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DSC2233FE1 参数 Datasheet PDF下载

DSC2233FE1图片预览
型号: DSC2233FE1
PDF下载: 下载PDF文件 查看货源
内容描述: [Low-Jitter I2C/SPI Programmable Dual LVDS Oscillator]
分类和应用:
文件页数/大小: 6 页 / 544 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
 浏览型号DSC2233FE1的Datasheet PDF文件第1页浏览型号DSC2233FE1的Datasheet PDF文件第2页浏览型号DSC2233FE1的Datasheet PDF文件第3页浏览型号DSC2233FE1的Datasheet PDF文件第5页浏览型号DSC2233FE1的Datasheet PDF文件第6页  
Low-Jitter I2C/SPI Programmable Dual LVDS Oscillator  
DSC2133 DSC2233  
Absolute Maximum Ratings  
Ordering Code  
Item  
Min  
Max  
Unit Condition  
Prog Mode  
1: I2C bus  
2: SPI bus  
Temp Range  
E: -20 to 70  
I: -40 to 85  
Packing  
T: Tape & Reel  
: Tube  
Supply Voltage  
-0.3  
+4.0  
V
Input Voltage  
Junction Temp  
Storage Temp  
Soldering Temp  
-0.3 VDD+0.3  
V
°C  
°C  
-
-55  
-
+150  
+150  
+260  
DSC2 1 33 F I 2  
xxxxx  
T
-
°C  
V
40sec max.  
ESD  
HBM  
MM  
-
Package  
F: 3.2x2.5mm  
Stability  
1: ±50ppm  
2: ±25ppm  
Freq (MHz)  
See Freq. table  
4000  
400  
CDM  
1500  
Note: 1000+ years of data retention on internal memory  
Specifications (Unless specified otherwise: T=25° C)  
Parameter  
Supply Voltage1  
Condition  
Min.  
Typ.  
Max.  
3.6  
Unit  
VDD  
IDD  
2.25  
V
Supply Current  
Supply Current2  
EN pin low outputs are disabled  
21  
38  
23  
mA  
EN pin high outputs are enabled  
RL=100Ω, FO1=FO2 =156.25 MHz  
Includes frequency variations due  
to initial tolerance, temp. and  
power supply voltage  
IDD  
mA  
±25  
±50  
Frequency Stability  
Aging  
Startup Time3  
Δf  
ppm  
Δf  
tSU  
1 year @25°C  
T=25°C  
±5  
5
ppm  
ms  
Input Logic Levels  
Input logic high  
Input logic low  
VIH  
VIL  
0.75xVDD  
-
-
V
0.25xVDD  
Output Disable Time4  
Output Enable Time  
Pull-Up Resistor2  
tDA  
5
ns  
ns  
tEN  
20  
Pull-up exists on all digital IO  
LVDS Outputs  
40  
kΩ  
Output Offset Voltage  
Delta Offset Voltage  
Pk to Pk Output Swing  
Output Transition time4  
Rise Time  
R=100Ω Differential  
1.125  
1.4  
50  
V
mV  
mV  
Single-Ended  
350  
200  
20% to 80%  
RL=50Ω, CL= 2pF  
tR  
tF  
ps  
Fall Time  
Frequency  
f0  
Single Frequency  
Differential  
2.3  
48  
460  
52  
MHz  
%
Output Duty Cycle  
Period Jitter5  
SYM  
JPER  
FO1=FO2=156.25 MHz  
2.5  
psRMS  
200kHz to 20MHz @148.5MHz  
100kHz to 20MHz @148.5MHz  
12kHz to 20MHz @148.5MHz  
0.28  
0.4  
1.7  
Integrated Phase Noise  
JCC  
psRMS  
2
Notes:  
1.  
Pin 4 VDD should be filtered with 0.01uf capacitor.  
2.  
3.  
4.  
5.  
Output is enabled if Enable pad is floated or not connected.  
tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled.  
Output Waveform and Test Circuit figures below define the parameters.  
Period Jitter includes crosstalk from adjacent output.  
______________________________________________________________________________________________________________________________________________  
DSC2133 DSC2233 Page 4 MK-Q-B-P-D-12050109