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DSC2211FL2-E0016T 参数 Datasheet PDF下载

DSC2211FL2-E0016T图片预览
型号: DSC2211FL2-E0016T
PDF下载: 下载PDF文件 查看货源
内容描述: [Crystal-less™ Configurable Clock Generator]
分类和应用:
文件页数/大小: 6 页 / 593 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
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Micrel, Inc.  
DSC2211FL2-E0016  
Operational Description  
The DSC2211FL2-E0016 is a dual output LVCMOS  
oscillator consisting of a MEMS resonator and a supporting  
PLL IC. The two LVCMOS outputs are generated through  
independent 8-bit programmable dividers from the output  
of the internal PLL. DSC2211FL2-E0016 allows for easy  
programming of theoutput frequencies using SPI interface.  
Upon power-up, the output frequencies are controlled  
by an internal pre-programmed memory (OTP). This  
memory stores all coefficients required by the PLL for two  
different default frequency pairs. The control pin (FS)  
selects the initial pair. Once the device is powered up, a  
new output frequency pair can be programmed using SPI  
pins. Programming details are provided in the  
Programming Guide.  
The DSC2211FL2-E0016 has independent control of the  
output voltage levels of the two outputs. The high voltage  
level of CLK1 is equal to the main supply voltage, VDD  
(pin 13). VDD2 (pin 12) sets the high voltage level of  
CLK2. VDD2 must be equal to or less than VDD at all  
times to insure proper operation. VDD2 can be as low  
as 1.65V. When OE (pin 1) is floated or connected to  
VDD, the DSC2211FL2-E0016 is in operational mode.  
Driving OE to ground will disable both output  
drivers (hi-impedance mode).  
DSC2211FL2-E0016 has programmable output drive  
strength, which can be controlled via SPI.  
Table 1 displays typical rise / fall times for the output  
with a 15pF load capacitance as a function of these  
control bits at VDD = 3.3V and room temperature.  
Output Drive Strength Bits [OXS2, OXS1, OXS0] - Default is [111] - X = 1 for CLK1, and 2 for CLK2  
000  
2.1  
2.5  
001  
1.7  
2.4  
010  
1.6  
2.4  
011  
1.4  
2
100  
1.3  
1.8  
101  
1.3  
1.6  
110  
1.2  
1.3  
111  
1.1  
1.3  
tr (ns)  
tf (ns)  
Table 1. Rise/Fall Times for Drive Strengths  
Output Clock Frequencies  
Frequency select bits are weakly tied high so if left unconnected the default setting will be [1] and the device will output the  
associated frequency highlighted in bold.  
Freq Select Bit [FS] - Default is [1]  
Freq (MHz)  
0
1
CLK1  
CLK2  
100  
25  
80  
80  
Table 2. Pin-Selectable Output Frequencies  
Absolute Maximum Ratings  
Item  
Min.  
-0.3  
-0.3  
-
Max.  
+4.0  
Units  
V
Condition  
Supply Voltage  
Input Voltage  
Junction Temp  
Storage Temp  
Soldering Temp  
VDD + 0.3  
+150  
V
°C  
°C  
°C  
-55  
-
+150  
+260  
40sec max.  
ESD  
HBM  
MM  
4000  
400  
-
V
CDM  
1500  
1000+ years of data retention on internal memory  
April 20, 2015  
2917  
3
Revision 1.0  
tcghelp@micrel.comor (408) 955-1690