Micrel, Inc.
DSC2211FL2-E0016
Specifications (Unless specified otherwise: T = 25°C, max LVCMOS drive strength)
Parameter
Symbol
Condition
Min.
2.25
1.65
Typ.
Max.
3.6
Units
V
Supply Voltage¹
VDD
Supply Voltage (CLK2)¹ VDD2
3.6
V
Supply Current
Supply Current²
IDD
IDD
OE pin low - outputs are disabled
21
32
23
mA
OE pin high - outputs are enabled
CL = 15pF, F01 = F02 = 125MHz
mA
Includes frequency variation due to initial
tolerance, temp. and power supply voltage
Frequency Stability
F
±25
ppm
Aging
F
First year (@ 25°C)
T = 25°C
±5
5
ppm
ms
Startup Time³
tSU
Input Logic Levels
Input Logic High
Input Logic Low
VIH
VIL
0.75 x VDD
-
-
0.25 x VDD
V
ns
Output Disable Time4
Output Enable Time
Pull-Up Resistor²
tDA
tEN
5
20
ns
Pull-up exists on all digital IO
40
kOhms
LVCMOS Outputs
Output Logic Levels
Output Logic High
Output Logic Low
VOH
VOL
I = ±6mA
0.9 x VDD
-
-
V
0.1 x VDD
Output Transition Time4
Rise Time
tR
tF
20% to 80%
CL = 15pF
1.1
1.4
2
2
Fall Time
ns
CLK1
CLK2
80
80
Frequency
[FS] = [1]
MHz
Output Duty Cycle
Period Jitter5
SYM
JPER
45
55
2
%
F01 = F02 = 125MHz
3
psRMS
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
0.3
0.38
1.7
Integrated Phase Noise
JPH
psRMS
Notes:
1. Pin 12 VDD2, and pin 13 VDD should be filtered with 0.1uF capacitors.
2. Output is enabled if OE pin is floated or not connected.
3. tSU is time to 100ppm stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform and Test Circuit figures below define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
April 20, 2015
2917
4
Revision 1.0
tcghelp@micrel.comor (408) 955-1690
MICREL [ MICREL SEMICONDUCTOR ]
