Micrel, Inc.
DSC2044FL1-H0005
Specifications (Unless specified otherwise: T = 25°C)
Parameter
Symbol
VDD
Condition
Min.
Typ.
Max.
3.6
Units
V
Supply Voltage¹
Supply Current
2.25
IDD
OE pin low - output is disabled
21
60
23
mA
OE pin high - outputs are enabled
RL = 50Ohms, F01 = F02 = 156.25MHz
Supply Current²
IDD
F
mA
Includes frequency variation due to initial
tolerance, temp. and power supply voltage
Frequency Stability
±50
ppm
Aging
F
First year (@ 25°C)
T = 25°C
±5
5
ppm
ms
Startup Time³
tSU
Input Logic Levels
Input Logic High
Input Logic Low
VIH
VIL
0.75 x VDD
-
-
V
0.25 x VDD
4
Output Disable Time
tDA
tEN
5
ns
ns
4
Output Enable Time
20
Pull-Up Resistor²
Pull-up exists on all digital IO
40
kOhms
HCSL Outputs
Output Logic Levels
Output Logic High
Output Logic Low
VOH
VOL
RL = 50Ohms
Single-Ended
0.725
-
-
0.1
V
mV
ps
Pk to Pk Output Swing
750
4
Output Transition Time
Rise Time
tR
tF
20% to 80%
RL = 50Ohms, CL = 2pF
200
48
400
52
Fall Time
CLK1
CLK2
125
125
Frequency
[FS2, FS1, FS0] = [1, 1, 1]
MHz
Output Duty Cycle
Period Jitter5
SYM
JPER
Differential
%
F01 = F02 = 156.25MHz
2.8
psRMS
200kHz to 20MHz @ 156.25MHz
100kHz to 20MHz @ 156.25MHz
12kHz to 20MHz @ 156.25MHz
0.25
0.37
1.7
Integrated Phase Noise
JPH
2
psRMS
Notes:
1. Pin 12 VDD2, and pin 13 VDD should be filtered with 0.1uF capacitors.
2. Output is enabled if OE pin is floated or not connected.
3. tSU is time to 100ppm stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform and Test Circuit figures below define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
March 01, 2016
3563
4
Revision 1.0
tcghelp@micrel.comor (408) 955-1690
MICREL [ MICREL SEMICONDUCTOR ]
