Low-Jitter Configurable HCSL-LVPECL Oscillator
DSC2042
Pin Description
Pin No.
Pin Name Pin Type
Description
Enables outputs when high and disables when low
Leave unconnected or grounded
Leave unconnected or grounded
Ground
1
2
3
Enable
NC
I
NA
NC
NA
4
GND
Power
5
6
7
8
FS0
FS1
FS2
I
I
I
O
O
Least significant bit for frequency selection
Middle bit for frequency selection
Most significant bit for frequency selection
Positive HCSL Output 1
Negative HCSL Output 1
Negative LVPECL Output 2
Positive LVPECL Output 2
Power Supply 2 for HCSL Output 2
Power Supply
Output1+
Output1-
Output 2-
Output 2+
VDD2
VDD
9
10
11
12
13
14
O
O
Power
Power
NA
NC
Leave unconnected or grounded
Operational Description
The DSC2042 is a dual oscillator with an HCSL
output and an LVPECL output. The device
consists of a MEMS resonator and a support
memory (OTP).
coefficients required by the PLL for up to eight
different frequency combinations. Three
control pins (FS0 – FS2) select the output
frequency combination. Discera supports
customer defined versions of the DSC2042.
Standard frequency options are described in in
the following sections.
This memory stores all
PLL IC.
The two outputs are generated
through independent 8-bit programmable
dividers from the output of the internal PLL.
Two constraints are imposed on the output
frequencies: 1) f2=M x f1/N, where M and N
are even integers between 4 and 254, 2)
1.2GHz < N x f2 < 1.7GHz.
When Enable (pin 1) is floated or connected to
VDD, the DSC2042 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
The actual frequencies output by the DSC2042
are controlled by an internal pre-programmed
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DSC2042 Page 2 MK-Q-B-P-D-12042612-2
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