Low-Jitter Configurable HCSL-LVPECL Oscillator
DSC2042
Specifications (Unless specified otherwise: T=25° C)
Parameter
Supply Voltage1
Condition
Min.
Typ.
Max.
3.6
Unit
V
VDD
IDD
2.25
Supply Current
Supply Current2
EN pin low – outputs are disabled
21
76
23
mA
EN pin high – outputs are enabled
RL=50Ω, FO1= FO2=156.25 MHz
IDD
mA
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
±10
±25
±50
±5
5
Frequency Stability
Aging
Startup Time3
Δf
ppm
Δf
tSU
1 year @25°C
T=25°C
ppm
ms
Input Logic Levels
Input logic high
Input logic low
VIH
VIL
0.75xVDD
-
-
V
0.25xVDD
Output Disable Time4
Output Enable Time
Pull-Up Resistor2
tDA
5
ns
ns
tEN
20
Pull-up exists on all digital IO
40
kΩ
LVPECL Outputs
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
RL=50Ω
VDD-1.08
-
-
V
VDD-1.55
Pk to Pk Output Swing
Output Transition time4
Rise Time
Single-Ended
800
250
mV
ps
20% to 80%
tR
tF
RL=50Ω
Fall Time
Frequency
f0
Single Frequency
Differential
2.3
48
460
52
MHz
%
Output Duty Cycle
Period Jitter5
SYM
JPER
FO1=125 MHz
2.5
psRMS
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.25
0.38
1.7
Integrated Phase Noise
JCC
psRMS
2
HCSL Outputs
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
RL=50Ω
0.725
-
-
0.1
V
Pk to Pk Output Swing
Single-Ended
750
mV
ps
Output Transition time4
Rise Time
20% to 80%
RL=50Ω, CL= 2pF
tR
tF
200
400
Fall Time
Frequency
f0
Single Frequency
Differential
2.3
48
460
52
MHz
%
Output Duty Cycle
SYM
Period Jitter5
JPER
JPH
FO1=FO2=156.25 MHz
2.8
psRMS
psRMS
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.25
0.37
1.7
Integrated Phase Noise
2
Notes:
1.
Pin 4 VDD should be filtered with 0.01uf capacitor.
2.
3.
4.
5.
Output is enabled if Enable pad is floated or not connected.
tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
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DSC2042 Page 4 MK-Q-B-P-D-12042612-2