Low-Jitter Configurable Dual HCSL-CMOS Oscillator
DSC2041
Pin Description
Pin
Type
I
NA
Pin No. Pin Name
Description
Enables outputs when high and disables (tri-state) them when low
Leave unconnected or grounded
1
2
Enable
NC
3
4
OS0
GND
I
Least significant bit for output drive strength selection for CMOS
Ground
Power
5
6
FS0
FS1
I
I
Least significant bit for frequency selection
Middle bit for frequency selection
7
8
9
10
11
12
13
14
FS2
I
O
O
I
O
Most significant bit for frequency selection
Positive HCSL Output 1
Negative HCSL Output 1
Middle bit for output drive strength selection for CMOS
CMOS output
Power Supply 2 for CMOS Output
Output1+
Output1-
OS1
Output 2
VDD2
VDD
Power
Power
Power Supply
OS2
I
Most significant bit for output drive strength selection for CMOS
Operational Description
The DSC2041 is a dual output HCSL-CMOS
oscillator consisting of a MEMS resonator and
a support PLL IC. The two outputs, CMOS and
HCSL, are generated through independent 8-
bit programmable dividers from the output of
the internal PLL. Two constraints are imposed
on the output frequencies: 1) f2=M x f1/N,
where M and N are even integers between 4
and 254, 2) 1.2GHz < N x f2 < 1.7GHz.
When Enable (pin 1) is floated or connected to
VDD, the DSC2041 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
The DSC2041 has programmable output drive
strength for CMOS output. Using three control
pins (OS0-OS2), the drive strength for CMOS
output (output 2) can be adjusted to match
circuit board impedances to reduce power
supply noise, overshoot/undershoot and EMI.
Table 1 displays typical rise / fall times for the
output with a 15pf load capacitance as a
function of these control pins at VDD=3.3V
and room temperature.
The actual frequencies output by the DSC2041
are controlled by an internal pre-programmed
memory (OTP).
coefficients required by the PLL for up to eight
different frequency combinations. Three
control pins (FS0 – FS2) select the output
frequency combination. Discera supports
This memory stores all
Table 1. Rise/Fall times for drive strengths
customer defined versions of the DSC2041.
Standard frequency options are described in in
the following sections.
Output Drive Strength Bits
[OS2, OS1, OS0] - Default [111]
000 001 010 011 100 101 110 111
tr (ns) 2.1 1.7 1.6 1.4 1.3 1.3 1.2 1.1
The DSC2041 provides control of the output
voltage levels of the CMOS output. VDD2 (pin
12) sets the high voltage level of Output 2 and
must be equal to or less than VDD at all times
to insure proper operation. VDD2 can be as
low as 1.65V.
tf (ns) 2.5 2.4 2.4
2
1.8 1.6 1.3 1.3
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DSC2041 Page 2 MK-Q-B-P-D-12042611-2
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