Low-Jitter Configurable Dual CMOS Oscillator
DSC2011
Absolute Maximum Ratings
Ordering Code
Item
Min
Max
Unit Condition
Temp Range
E: -20 to 70
I: -40 to 85
L: -40 to 105
M: -55 to 125
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
-0.3
+4.0
V
V
Packing
T: Tape & Reel
: Tube
-0.3 VDD+0.3
-
-55
-
+150
+150
+260
°C
°C
°C
V
DSC2011 F I 2
xxxxx
T
40sec max.
ESD
HBM
MM
-
Package
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
Freq (MHz)
See Freq. table
4000
400
1500
F: 3.2x2.5mm
CDM
Note: 1000+ years of data retention on internal memory
Specifications (Unless specified otherwise: T=25° C, max CMOS drive strength)
Parameter
Supply Voltage1
Supply Current
Supply Current2
Condition
Min.
2.25
Typ.
Max.
3.6
23
Unit
V
mA
VDD
IDD
EN pin low – outputs are disabled
21
32
EN pin high – outputs are enabled
CL=15pF, FO1=FO2=125 MHz
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
IDD
mA
±10
±25
±50
±5
5
Frequency Stability
Aging
Startup Time3
Δf
ppm
Δf
tSU
1 year @25°C
T=25°C
ppm
ms
Input Logic Levels
Input logic high
Input logic low
VIH
VIL
0.75xVDD
-
-
V
0.25xVDD
Output Disable Time4
Output Enable Time
Pull-Up Resistor2
tDA
5
ns
ns
tEN
20
Pull-up exists on all digital IO
40
kΩ
CMOS Outputs
Output Logic Levels
Output logic high
Output logic low
Output Transition time4
Rise Time
VOH
VOL
0.9xVDD
-
-
V
I=±6mA
0.1xVDD
20% to 80%
CL=15pf
tR
tF
1.1
1.4
2
2
ns
Fall Time
Commercial/Industrial temp range
Automotive temp range
2.3
45
170
100
55
Frequency
f0
MHz
Output Duty Cycle
Period Jitter5
SYM
JPER
%
psRMS
FO1=FO2=125 MHz
3
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
0.3
0.38
1.7
Integrated Phase Noise
JCC
psRMS
2
Notes:
1.
Pin 4 VDD should be filtered with 0.01uf capacitor.
2.
3.
4.
5.
Output is enabled if Enable pad is floated or not connected.
tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
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DSC2011 Page 4 MK-Q-B-P-D-12042602-2