Low-Jitter Configurable CMOS Oscillator
DSC2010
Absolute Maximum Ratings
Ordering Code
Item
Min
Max
Unit Condition
Temp Range
E: -20 to 70
I: -40 to 85
L: -40 to 105
M: -55 to 125
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
-0.3
+4.0
V
V
Packing
T: Tape & Reel
: Tube
-0.3 VDD+0.3
-
-55
-
+150
+150
+260
°C
°C
°C
V
DSC2010 F I 2
xxxxx
T
40sec max.
ESD
HBM
MM
-
Package
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
Freq (MHz)
See Freq. table
4000
400
1500
F: 3.2x2.5mm
CDM
Note: 1000+ years of data retention on internal memory
Specifications (Unless specified otherwise: T=25° C, max CMOS drive strength)
Parameter
Supply Voltage1
Condition
Min.
Typ.
Max.
Unit
V
VDD
IDD
2.25
3.6
23
Supply Current
EN pin low – output is disabled
21
mA
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
±10
±25
±50
Frequency Stability
Δf
ppm
Aging
Startup Time2
Δf
tSU
1 year @25°C
T=25°C
±5
5
ppm
ms
Input Logic Levels
Input logic high
Input logic low
VIH
VIL
0.75xVDD
-
-
V
0.25xVDD
Output Disable Time3
Output Enable Time
Pull-Up Resistor4
tDA
5
ns
ns
tEN
20
Pull-up exists on all digital IO
40
31
kΩ
CMOS Output
EN pin high – output is enabled
Supply Current4
IDD
35
mA
V
CL=15pF, FO=125 MHz
Output Logic Levels
Output logic high
Output logic low
Output Transition time3
Rise Time
VOH
VOL
I=±6mA
0.9xVDD
-
-
0.1xVDD
20% to 80%
CL=15pf
tR
tF
1.1
1.3
2
2
ns
Fall Time
Commercial/Industrial temp range
Automotive temp range
2.3
45
170
100
Frequency
f0
MHz
Output Duty Cycle
Period Jitter
SYM
JPER
55
2
%
FO=125 MHz
3
psRMS
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
0.3
0.38
1.7
Integrated Phase Noise
JCC
psRMS
Notes:
1.
Pin 4 VDD should be filtered with 0.01uf capacitor.
2.
3.
4.
tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Output is enabled if Enable pad is floated or not connected.
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DSC2010 Page 4 MK-Q-B-P-D-12042601-2