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DSC1124NL5 参数 Datasheet PDF下载

DSC1124NL5图片预览
型号: DSC1124NL5
PDF下载: 下载PDF文件 查看货源
内容描述: [Low-Jitter Precision HCSL Oscillator]
分类和应用:
文件页数/大小: 7 页 / 563 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
 浏览型号DSC1124NL5的Datasheet PDF文件第1页浏览型号DSC1124NL5的Datasheet PDF文件第3页浏览型号DSC1124NL5的Datasheet PDF文件第4页浏览型号DSC1124NL5的Datasheet PDF文件第5页浏览型号DSC1124NL5的Datasheet PDF文件第6页浏览型号DSC1124NL5的Datasheet PDF文件第7页  
Low-Jitter Precision HCSL Oscillator  
DSC1104 DSC1124  
Absolute Maximum Ratings  
Ordering Code  
Item  
Min  
-0.3  
-0.3  
-
Max  
+4.0  
Unit Condition  
Temp Range  
E: -20 to 70  
I: -40 to 85  
L: -40 to 105  
Supply Voltage  
Input Voltage  
Junction Temp  
Storage Temp  
Soldering Temp  
V
V
Enable Modes  
0: Enable/Standby  
2: Enable/Disable  
Packing  
T: Tape & Reel  
: Tube  
VDD+0.3  
+150  
°C  
°C  
°C  
V
-55  
-
+150  
DSC11 0 4 C I 5  
125.0000  
T
-
+260  
40sec max.  
ESD  
HBM  
MM  
-
Package  
A: 7.0x5.0mm  
B: 5.0x3.2mm  
C: 3.2x2.5mm  
Stability  
1: ±50ppm  
2: ±25ppm  
5: ±10ppm  
Freq (MHz)  
125.0000  
4000  
400  
CDM  
1500  
D: 2.5x2.0mm  
N: 7.0x5.0mm (no center pad)  
Note: 1000+ years of data retention on internal memory  
Specifications  
Parameter  
Condition  
Min.  
Typ.  
Max.  
Unit  
Supply Voltage1  
VDD  
IDD  
2.25  
3.6  
V
EN pin low outputs are disabled  
Supply Current  
DSC1104  
DSC1124  
0.095  
22  
mA  
20  
Includes frequency variations due  
to initial tolerance, temp. and  
power supply voltage  
±10  
±25  
±50  
Frequency Stability  
Δf  
ppm  
Aging  
Startup Time2  
Δf  
tSU  
1 year @25°C  
T=25°C  
±5  
5
ppm  
ms  
Input Logic Levels  
Input logic high  
Input logic low  
VIH  
VIL  
0.75xVDD  
-
-
V
0.25xVDD  
Output Disable Time3  
Output Enable Time  
Enable Pull-Up Resistor4  
tDA  
5
ns  
DSC1104  
DSC1124  
5
20  
ms  
ns  
tEN  
Pull-up resistor exist  
HCSL Outputs  
40  
40  
kΩ  
Supply Current  
IDD  
Output Enabled, RL=50Ω  
42  
mA  
V
Output Logic Levels  
Output logic high  
Output logic low  
VOH  
VOL  
RL=50Ω  
0.725  
-
-
0.1  
Pk to Pk Output Swing  
Output Transition time3  
Rise Time  
Single-Ended  
750  
mV  
ps  
20% to 80%  
RL=50Ω, CL= 2pF  
tR  
tF  
200  
400  
Fall Time  
Frequency  
f0  
Single Frequency  
Differential  
2.3  
48  
460  
52  
MHz  
%
Output Duty Cycle  
Period Jitter  
SYM  
JPER  
2.5  
psRMS  
200kHz to 20MHz @156.25MHz  
100kHz to 20MHz @156.25MHz  
12kHz to 20MHz @156.25MHz  
0.25  
0.37  
1.7  
Integrated Phase Noise  
JPH  
psRMS  
2
Notes:  
1.  
Pin 6 VDD should be filtered with 0.1uf capacitor.  
2.  
3.  
4.  
tsu is time to 100ppm of output frequency after VDD is applied and outputs are enabled.  
Output Waveform and Test Circuit figures below define the parameters.  
Output is enabled if pad is floated or not connected.  
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DSC1104 | DSC1124 Page 2 MK-Q-B-P-D-110410-04-6