欢迎访问ic37.com |
会员登录 免费注册
发布采购

DSC1121NL2 参数 Datasheet PDF下载

DSC1121NL2图片预览
型号: DSC1121NL2
PDF下载: 下载PDF文件 查看货源
内容描述: [Low-Jitter Precision CMOS Oscillator]
分类和应用:
文件页数/大小: 7 页 / 697 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
 浏览型号DSC1121NL2的Datasheet PDF文件第1页浏览型号DSC1121NL2的Datasheet PDF文件第3页浏览型号DSC1121NL2的Datasheet PDF文件第4页浏览型号DSC1121NL2的Datasheet PDF文件第5页浏览型号DSC1121NL2的Datasheet PDF文件第6页浏览型号DSC1121NL2的Datasheet PDF文件第7页  
Low-Jitter Precision CMOS Oscillator  
DSC1101 DSC1121  
Absolute Maximum Ratings  
Ordering Code  
Item  
Min  
-0.3  
-0.3  
-
Max  
+4.0  
Unit Condition  
Temp Range  
E: -20 to 70  
I: -40 to 85  
L: -40 to 105  
M: -55 to 125  
Supply Voltage  
Input Voltage  
Junction Temp  
Storage Temp  
Soldering Temp  
V
V
Enable Modes  
0: Enable/Standby  
2: Enable/Disable  
Packing  
T: Tape & Reel  
: Tube  
VDD+0.3  
+150  
°C  
°C  
-55  
-
+150  
DSC11 0 1 C I 5  
125.0000  
T
-
+260  
°C  
V
40sec max.  
ESD  
HBM  
MM  
-
Package  
A: 7.0x5.0mm  
B: 5.0x3.2mm  
C: 3.2x2.5mm  
Stability  
1: ±50ppm  
2: ±25ppm  
5: ±10ppm  
Freq (MHz)  
125.0000  
4000  
400  
1500  
CDM  
D: 2.5x2.0mm  
N: 7.0x5.0mm (no center pad)  
Note: 1000+ years of data retention on internal memory  
Specifications  
Parameter  
Condition  
Min.  
Typ.  
Max.  
Unit  
Supply Voltage1  
VDD  
IDD  
2.25  
3.6  
V
EN pin low output is disabled  
DSC1101  
Supply Current  
0.095  
22  
mA  
DSC1121  
20  
Frequency Stability  
Ext Comm. & Ind. only  
All temp ranges  
Includes frequency variations due  
to initial tolerance, temp. and  
power supply voltage  
±10  
±25  
±50  
Δf  
ppm  
All temp ranges  
Aging  
Startup Time2  
Δf  
tSU  
1 year @25°C  
T=25°C  
±5  
5
ppm  
ms  
Input Logic Levels  
Input logic high  
Input logic low  
VIH  
VIL  
0.75xVDD  
-
-
V
0.25xVDD  
Output Disable Time3  
Output Enable Time  
Enable Pull-Up Resistor4  
tDA  
5
ns  
DSC1101  
DSC1121  
5
20  
ms  
ns  
tEN  
Pull-up resistor exist  
40  
31  
kΩ  
CMOS Output  
output is enabled  
CL=15pF, F0=125 MHz  
Supply Current4  
IDD  
35  
mA  
V
Output Logic Levels  
Output logic high  
Output logic low  
Output Transition time3  
Rise Time  
VOH  
VOL  
I=±6mA  
0.9xVDD  
-
-
0.1xVDD  
20% to 80%  
CL=15pF  
tR  
tF  
1.1  
1.3  
2
2
ns  
Fall Time  
All temp range except Auto  
Auto temp range  
2.3  
45  
170  
100  
Frequency  
f0  
MHz  
%
Output Duty Cycle  
Period Jitter  
SYM  
JPER  
55  
Fout=125MHz  
3
psRMS  
200kHz to 20MHz @ 125MHz  
100kHz to 20MHz @ 125MHz  
12kHz to 20MHz @ 125MHz  
0.3  
0.38  
1.7  
Integrated Phase Noise  
JPH  
psRMS  
2
1.  
2.  
3.  
4.  
Pin 6 VDD should be filtered with 0.1uf capacitor.  
tsu is time to 100PPM of output frequency after VDD is applied and outputs are enabled.  
Output Waveform and Test Circuit figures below define the parameters.  
Output is enabled if pad is floated or not connected.  
______________________________________________________________________________________________________________________________________________  
DSC1101 | DSC1121 Page 2 MK-Q-B-P-D-110410-01-6