1.8~3.3V
Low-Power Precision CMOS Oscillator
DSC1001
VDD = 1.8v
Parameter
Symbol
Condition
1MHz
Min
Typ
6.0
6.5
7.2
8.3
Max
6.3
6.9
7.5
9.1
Unit
CL=0p
RL=∞
T=25°C
27MHz
70MHz
150MHz
Supply Current, no load
IDD
mA
Output Transition time
Rise Time
Fall Time
tR
tF
CL=15pF; T=25°C
20%/80%*VDD
1.8
1.0
3
3
ns
Ps
Jitter, Max Cycle to Cycle
JCC
F = 100MHz3
60
VDD = 2.5v
Parameter
Symbol
Condition
Min
Typ
6.0
6.7
7.7
9.6
Max
6.3
7.0
8.1
10.6
Unit
1MHz
CL=0p
RL=∞
T=25°C
27MHz
70MHz
150MHz
Supply Current, no load
IDD
mA
Output Transition time
Rise Time
Fall Time
tR
tF
CL=15pF; T=25°C
20%/80%*VDD
1.0
0.9
2
2
ns
ps
Jitter, Max Cycle to Cycle
JCC
F = 100MHz3
50
VDD = 3.3v
Parameter
Symbol
Condition
Min
Typ
6.0
6.8
8.2
10.8
Max
6.3
7.2
8.7
12.2
Unit
1MHz
CL=0p
RL=∞
T=25°C
27MHz
70MHz
150MHz
Supply Current, no load
IDD
mA
Output Transition time
Rise Time
Fall Time
tR
tF
JCC
CL=15pF; T=25°C
20%/80%*VDD
1.0
0.9
50
2
2
ns
ps
Jitter, Max Cycle to Cycle
F = 100MHz3
Notes:
1.
Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be
operated beyond these limits.
2.
3.
tSU is time to stable output frequency after VDD is applied. tSU and tEN (after Standby# is asserted high) are identical values.
Measured over 50k clock cycles.
MK-Q-B-P-D-050610-01-9
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