WME128K8-XXX
READ
Figure 3 shows Read cycle waveforms. A read cycle begins with
selection address, chip select and output enable. Chip select is
accomplished by placing the CS# line low. Output enable is done
by placing the OE# line low. The memory places the selected data
byte on I/O0 through I/O7 after the access time. The output of the
memory is placed in a high impedance state shortly after either
the OE# line or CS# line is returned to a high level.
FIGURE 3 – READ WAVEFORMS
t RC
ADDRESS VALID
ADDRESS
CS#
tACS
tOE
OE#
tDF
tACC
t OH
HIGH Z
OUTPUT
VALID
OUTPUT
NOTE:
OE# may be delayed up to tACS- tOE after the falling edge of CS#
without impact on tOE or by tACC- tOE after an address change without impact on tACC.
AC READ CHARACTERISTICS (See Figure 3)
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
-125
-140
-150
-200
-250
-300
Read Cycle Parameter
Read Cycle Time
Symbol
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tRC
tACC
tACS
125
140
150
200
250
300
ns
ns
ns
Address Access Time
125
125
140
140
150
150
200
200
250
250
300
300
Chip Select Access Time
Output Hold from Address Change, OE#
or CS#
tOH
0
0
0
0
0
0
ns
Output Enable to Output Valid
tOE
tDF
55
63
55
70
55
70
55
70
85
70
85
70
ns
ns
Chip Select or OE# to High Z Output
3
4311.11E-0718-ss-WME128K8-XXX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
